OTBN Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: `edf2fd5092`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	330.228us	1	1	100.00
V1	single_binary	otbn_single	28.017m	9.197ms	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	10.000s	106.741us	5	5	100.00
V1	csr_rw	otbn_csr_rw	11.000s	39.444us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	13.000s	122.947us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	21.759us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	216.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	11.000s	39.444us	20	20	100.00
		otbn_csr_aliasing	8.000s	21.759us	5	5	100.00
V1	mem_walk	otbn_mem_walk	48.000s	1.324ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	359.097us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	50.000s	269.530us	10	10	100.00
V2	multi_error	otbn_multi_err	52.000s	141.102us	1	1	100.00
V2	back_to_back	otbn_multi	10.867m	3.144ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.633m	272.707us	10	10	100.00
V2	lc_escalation	otbn_escalate	43.000s	599.087us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	32.609us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	26.000s	83.761us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	23.333us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	33.258us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	282.751us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	282.751us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	10.000s	106.741us	5	5	100.00
		otbn_csr_rw	11.000s	39.444us	20	20	100.00
		otbn_csr_aliasing	8.000s	21.759us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	26.866us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	10.000s	106.741us	5	5	100.00
		otbn_csr_rw	11.000s	39.444us	20	20	100.00
		otbn_csr_aliasing	8.000s	21.759us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	26.866us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	11.000s	44.194us	10	10	100.00
		otbn_dmem_err	19.000s	61.866us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	34.000s	133.930us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	57.232us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	232.268us	5	5	100.00
		otbn_urnd_err	11.000s	58.249us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	18.320us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	13.383us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	43.525us	7	10	70.00
V2S	tl_intg_err	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
		otbn_tl_intg_err	33.000s	200.059us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.150m	427.778us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	330.228us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	61.866us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	44.194us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	33.000s	200.059us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	43.000s	599.087us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	44.194us	10	10	100.00
		otbn_dmem_err	19.000s	61.866us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	32.609us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	18.320us	5	5	100.00
		otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	44.194us	10	10	100.00
		otbn_dmem_err	19.000s	61.866us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	32.609us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	18.320us	5	5	100.00
		otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	43.000s	599.087us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	44.194us	10	10	100.00
		otbn_dmem_err	19.000s	61.866us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	32.609us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	18.320us	5	5	100.00
		otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	16.000s	69.462us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	36.070us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	31.000s	317.284us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	31.000s	317.284us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	90.941us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	72.458us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	90.497us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	13.000s	90.497us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	9.000s	59.711us	3	7	42.86
V2S	sec_cm_data_mem_sec_wipe	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	10.867m	3.144ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	66.167us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	28.017m	9.197ms	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.100m	12.633ms	5	5	100.00
V2S		TOTAL			154	163	94.48
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	8.033m	5.249ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			571	585	97.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	10	90.91
V2S	20	20	16	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.62	95.67	99.71	93.58	92.35	100.00	98.83	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 7 failures:

Test otbn_sec_wipe_err has 4 failures.

1.otbn_sec_wipe_err.103060796324041438101117978227650031988074517745405091491855593833704261560226
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 50520976 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  50520976 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  50520976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.38443538760980961331796663958037990372142451941858745721661765891445129788690
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 59710590 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  59710590 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  59710590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test otbn_stack_addr_integ_chk has 1 failures.

2.otbn_stack_addr_integ_chk.110911889849158018030055416966887011373539479191334152299534591678070955719764
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 7207083 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   7207083 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   7207083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

7.otbn_escalate.82743867678097085614237770119803267697824584529260566646429001509495004390703
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 40906425 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  40906425 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  40906425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

8.otbn_ctrl_redun.115643370174111327592993414637689862147178704802033085655377622226372634208788
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 17089418 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  17089418 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  17089418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 3 failures:

Test otbn_partial_wipe has 2 failures.

2.otbn_partial_wipe.89223759276468590400184495487930068619277938161197391481359160220602662892735
Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14533330 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14533330 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14533330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_partial_wipe.104191750985075033434204660877863868283714990083096851161058858352237062840842
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 9007575 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   9007575 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   9007575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_single has 1 failures.

71.otbn_single.97347117622374536309102816700312243269056835449012888506800288991716256791161
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/71.otbn_single/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 127196249 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 127196249 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 127196249 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 127196249 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 127196249 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 2 failures:
- Test otbn_partial_wipe has 1 failures.
  - 6.otbn_partial_wipe.88017534363129533169696003397403037368332354382602119160247167698295825245949
    Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 13208808 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  13208808 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  13208808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.104775090982960152362786871376093755648659509315596106601234008060873420839267
    Line 396, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 875699034 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @ 875699034 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @ 875699034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.39175874981712084453279388500344997632112828991516716520037470257132999442009
    Line 395, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 198769142 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 198769142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 52.otbn_escalate.81549549468478679698511221583652998024426231130384126330514397156894837573957
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/52.otbn_escalate/latest/run.log
```
  UVM_ERROR @   5296325 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5296325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```