OTBN Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	17.000s	54.643us	1	1	100.00
V1	single_binary	otbn_single	4.583m	1.269ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	11.000s	46.378us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	12.800us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	786.073us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	19.839us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	74.556us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	12.800us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.839us	5	5	100.00
V1	mem_walk	otbn_mem_walk	44.000s	914.261us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	546.395us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	40.000s	320.852us	10	10	100.00
V2	multi_error	otbn_multi_err	48.000s	1.157ms	1	1	100.00
V2	back_to_back	otbn_multi	1.367m	938.332us	10	10	100.00
V2	stress_all	otbn_stress_all	1.967m	4.116ms	10	10	100.00
V2	lc_escalation	otbn_escalate	1.783m	434.803us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	28.872us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	31.000s	120.809us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	22.946us	50	50	100.00
V2	intr_test	otbn_intr_test	7.000s	18.495us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	93.595us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	93.595us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	11.000s	46.378us	5	5	100.00
		otbn_csr_rw	6.000s	12.800us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.839us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	39.221us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	11.000s	46.378us	5	5	100.00
		otbn_csr_rw	6.000s	12.800us	20	20	100.00
		otbn_csr_aliasing	6.000s	19.839us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	39.221us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	11.000s	40.882us	10	10	100.00
		otbn_dmem_err	13.000s	17.051us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	16.000s	76.008us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	57.080us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	116.648us	5	5	100.00
		otbn_urnd_err	9.000s	34.037us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	35.963us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	31.631us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	44.564us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
		otbn_tl_intg_err	31.000s	203.939us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.033m	347.390us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	17.000s	54.643us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	17.051us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	40.882us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	203.939us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.783m	434.803us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	40.882us	10	10	100.00
		otbn_dmem_err	13.000s	17.051us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	28.872us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	35.963us	5	5	100.00
		otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	40.882us	10	10	100.00
		otbn_dmem_err	13.000s	17.051us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	28.872us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	35.963us	5	5	100.00
		otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.783m	434.803us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	40.882us	10	10	100.00
		otbn_dmem_err	13.000s	17.051us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	28.872us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	35.963us	5	5	100.00
		otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	23.832us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	25.144us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.200m	136.367us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.200m	136.367us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	51.063us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	64.688us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	41.226us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	41.226us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	18.000s	113.103us	3	7	42.86
V2S	sec_cm_data_mem_sec_wipe	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.367m	938.332us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	47.000s	209.293us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	4.583m	1.269ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.633m	3.771ms	3	5	60.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	34.517m	9.936ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			574	585	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.92	99.61	95.49	99.69	93.41	93.09	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_sec_wipe_err has 4 failures.

1.otbn_sec_wipe_err.94364909468142808591409834305291002830876059220714674146537409037049306533692
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 113103385 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 113103385 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 113103385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_wipe_err.10277698231709743632170235212709223889509278348309767054218417612954659895090
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9498786 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   9498786 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   9498786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test otbn_escalate has 1 failures.

33.otbn_escalate.58376628191199232908404998348023382472365768301348567573193560266206852477455
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 54409809 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  54409809 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  54409809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.109300489933924438604505585418878197534250614205149986834441024556309506436514
Line 318, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 94533132 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 94533132 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 94533132 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 94533132 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 94533132 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

3.otbn_sec_cm.55386559866732292387472375692472695168482352779731546436378607291770919969761
Line 341, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 137129863 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 137129863 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 137129863 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 137129863 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 137129863 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 6.otbn_stress_all_with_rand_reset.70447516564617619723367654351802735947761709842780924291362440819530898234847
    Line 561, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1123949754 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1123949754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otbn_stress_all_with_rand_reset.90224549692365580482668261766009678567329807958520414793764579836985811217136
    Line 625, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9936041760 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9936041760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:486) [otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 4.otbn_stress_all_with_rand_reset.1281020771808468941908398414408152020065467725049977572193838823121266307719
    Line 732, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 34644124720 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 34644124720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 6.otbn_partial_wipe.55735282289215385975959818757184366627253940366159165359634552276039976405018
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 4514669 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   4514669 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   4514669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```