OTBN Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	127.585us	1	1	100.00
V1	single_binary	otbn_single	47.000s	218.404us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	57.137us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	18.200us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	118.663us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	34.365us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	48.237us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	18.200us	20	20	100.00
		otbn_csr_aliasing	6.000s	34.365us	5	5	100.00
V1	mem_walk	otbn_mem_walk	51.000s	2.425ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	3.166ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	42.000s	514.467us	10	10	100.00
V2	multi_error	otbn_multi_err	1.117m	1.910ms	1	1	100.00
V2	back_to_back	otbn_multi	1.650m	363.893us	10	10	100.00
V2	stress_all	otbn_stress_all	2.617m	2.254ms	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	57.021us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	62.976us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	29.000s	92.622us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	35.502us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	24.205us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	59.775us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	59.775us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	57.137us	5	5	100.00
		otbn_csr_rw	6.000s	18.200us	20	20	100.00
		otbn_csr_aliasing	6.000s	34.365us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	90.507us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	57.137us	5	5	100.00
		otbn_csr_rw	6.000s	18.200us	20	20	100.00
		otbn_csr_aliasing	6.000s	34.365us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	90.507us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	1.133m	266.415us	10	10	100.00
		otbn_dmem_err	21.000s	74.236us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	26.716us	5	5	100.00
		otbn_controller_ispr_rdata_err	1.083m	916.102us	5	5	100.00
		otbn_mac_bignum_acc_err	11.000s	231.716us	5	5	100.00
		otbn_urnd_err	8.000s	149.742us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	17.190us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	164.693us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	40.095us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
		otbn_tl_intg_err	23.000s	113.600us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.267m	470.017us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	127.585us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	21.000s	74.236us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	1.133m	266.415us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	23.000s	113.600us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	57.021us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	1.133m	266.415us	10	10	100.00
		otbn_dmem_err	21.000s	74.236us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	62.976us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	17.190us	5	5	100.00
		otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	1.133m	266.415us	10	10	100.00
		otbn_dmem_err	21.000s	74.236us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	62.976us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	17.190us	5	5	100.00
		otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	57.021us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	1.133m	266.415us	10	10	100.00
		otbn_dmem_err	21.000s	74.236us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	62.976us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	17.190us	5	5	100.00
		otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	16.000s	182.562us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	32.294us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.033m	227.095us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.033m	227.095us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	53.628us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	13.000s	68.119us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	21.000s	76.834us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	21.000s	76.834us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	25.779us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.650m	363.893us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	30.083us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	47.000s	218.404us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.017m	7.729ms	5	5	100.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.017m	2.001ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			578	585	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.89	99.60	95.40	99.68	93.41	92.82	94.87	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_ctrl_redun has 1 failures.

2.otbn_ctrl_redun.111451194889812812023992503467920151717999877543493227836196820949115520310019
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 4951667 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 4951667 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   4951667 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   4951667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 1 failures.

5.otbn_sec_wipe_err.52806383852969570913154643229381989723213795147955303897295750291542802157588
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25778534 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  25778534 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  25778534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

24.otbn_escalate.66738284464183665713847245170246809177479152692504774057613030461982049701406
Line 292, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13290339 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13290339 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  13290339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.56486888087301174616780602325358931616718404530353611787908057589873125396941
    Line 843, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7105647807 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7105647807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 2.otbn_partial_wipe.10165779711605655381275522747815671300191707914119276146149322058327234131588
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 14270057 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  14270057 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  14270057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 7.otbn_escalate.96597946378276886798023107795365965629979696935799630307145737817198672622566
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_escalate/latest/run.log
```
  UVM_FATAL @  83025853 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  83025853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 7.otbn_partial_wipe.57762213279421996306959383681229658037260618451637104513384164438656319809954
    Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 21231726 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  21231726 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  21231726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```