OTBN Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	148.007us	1	1	100.00
V1	single_binary	otbn_single	3.633m	1.034ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	16.052us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	13.887us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	111.632us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	15.324us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	65.629us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	13.887us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.324us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	3.655ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	490.621us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.967m	777.614us	10	10	100.00
V2	multi_error	otbn_multi_err	51.000s	520.332us	1	1	100.00
V2	back_to_back	otbn_multi	2.850m	436.388us	10	10	100.00
V2	stress_all	otbn_stress_all	4.550m	1.317ms	9	10	90.00
V2	lc_escalation	otbn_escalate	23.000s	140.362us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	67.718us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	100.512us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	81.284us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	12.944us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	19.763us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	19.763us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	16.052us	5	5	100.00
		otbn_csr_rw	6.000s	13.887us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.324us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	27.046us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	16.052us	5	5	100.00
		otbn_csr_rw	6.000s	13.887us	20	20	100.00
		otbn_csr_aliasing	6.000s	15.324us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	27.046us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	17.000s	56.727us	10	10	100.00
		otbn_dmem_err	13.000s	211.371us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	34.000s	126.009us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	217.275us	5	5	100.00
		otbn_mac_bignum_acc_err	19.000s	62.512us	5	5	100.00
		otbn_urnd_err	8.000s	53.396us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	21.036us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	24.814us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	26.220us	6	10	60.00
V2S	tl_intg_err	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
		otbn_tl_intg_err	52.000s	352.373us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	29.000s	328.261us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	148.007us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	211.371us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	56.727us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	52.000s	352.373us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	23.000s	140.362us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	56.727us	10	10	100.00
		otbn_dmem_err	13.000s	211.371us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	67.718us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	21.036us	5	5	100.00
		otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	56.727us	10	10	100.00
		otbn_dmem_err	13.000s	211.371us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	67.718us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	21.036us	5	5	100.00
		otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	23.000s	140.362us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	56.727us	10	10	100.00
		otbn_dmem_err	13.000s	211.371us	15	15	100.00
		otbn_zero_state_err_urnd	8.000s	67.718us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	21.036us	5	5	100.00
		otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	181.174us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	24.506us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	46.000s	129.053us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	46.000s	129.053us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	19.000s	200.024us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	62.990us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	46.000s	425.633us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	46.000s	425.633us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	27.552us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.850m	436.388us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	58.532us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.633m	1.034ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.433m	4.658ms	5	5	100.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	39.517m	53.401ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			574	585	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.61	95.49	99.70	93.38	92.86	100.00	98.83	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 0.otbn_stress_all_with_rand_reset.64626576074008999266033924855797750076150140505410713506247756903309146239548
    Line 381, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 669327632 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 669327632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stress_all_with_rand_reset.3979345377400246295361313791950496409749767288769539778870467478105535244642
    Line 572, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9722256357 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9722256357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 3 failures:

Test otbn_partial_wipe has 3 failures.

5.otbn_partial_wipe.21297034001031211983901565065693839334854845544460617388720881187446946607304
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 17910669 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  17910669 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  17910669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.otbn_partial_wipe.88912772212069147999400160808312399395324015478315454667579604004738526446648
Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 13961895 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  13961895 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  13961895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 0.otbn_sec_wipe_err.107677929033807356909032867873173321529088811951498484697583380870230304413969
    Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 27551840 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  27551840 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  27551840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 1.otbn_partial_wipe.49921837233296317701949641653138257274895692636237124252308902177181137258811
    Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 26220063 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  26220063 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  26220063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all has 1 failures.
  - 4.otbn_stress_all.15777798007330339832390473138968319850497276817679632257011036740545530868672
    Line 372, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all/latest/run.log
```
  UVM_FATAL @ 1317397704 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @ 1317397704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.98808193871895989029270796684780025428755820711963100637470554005739388779674
    Line 379, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 738553434 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @ 738553434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 39.otbn_escalate.73208830914126845939629483182909019708584208492438252919028717206622183538415
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/39.otbn_escalate/latest/run.log
```
  UVM_ERROR @   2378466 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   2378466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```