OTBN Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	74.272us	1	1	100.00
V1	single_binary	otbn_single	52.000s	802.533us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	29.224us	5	5	100.00
V1	csr_rw	otbn_csr_rw	17.000s	38.784us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	95.894us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	76.948us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	15.000s	64.468us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	17.000s	38.784us	20	20	100.00
		otbn_csr_aliasing	6.000s	76.948us	5	5	100.00
V1	mem_walk	otbn_mem_walk	39.000s	353.355us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	25.000s	486.259us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	47.000s	258.005us	10	10	100.00
V2	multi_error	otbn_multi_err	49.000s	1.277ms	1	1	100.00
V2	back_to_back	otbn_multi	1.683m	1.056ms	10	10	100.00
V2	stress_all	otbn_stress_all	25.133m	12.247ms	9	10	90.00
V2	lc_escalation	otbn_escalate	1.250m	27.955us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	17.000s	38.583us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	4.317m	1.151ms	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	162.513us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	11.696us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	12.000s	46.896us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	12.000s	46.896us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	29.224us	5	5	100.00
		otbn_csr_rw	17.000s	38.784us	20	20	100.00
		otbn_csr_aliasing	6.000s	76.948us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	33.495us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	29.224us	5	5	100.00
		otbn_csr_rw	17.000s	38.784us	20	20	100.00
		otbn_csr_aliasing	6.000s	76.948us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	33.495us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	23.000s	58.835us	10	10	100.00
		otbn_dmem_err	26.000s	65.811us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	1.317m	144.021us	5	5	100.00
		otbn_controller_ispr_rdata_err	28.000s	835.979us	5	5	100.00
		otbn_mac_bignum_acc_err	12.000s	116.655us	5	5	100.00
		otbn_urnd_err	7.000s	51.243us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	19.000s	47.164us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	12.000s	13.578us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	17.000s	308.975us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
		otbn_tl_intg_err	29.000s	190.871us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	232.461us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	74.272us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	26.000s	65.811us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	23.000s	58.835us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	29.000s	190.871us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.250m	27.955us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	23.000s	58.835us	10	10	100.00
		otbn_dmem_err	26.000s	65.811us	15	15	100.00
		otbn_zero_state_err_urnd	17.000s	38.583us	5	5	100.00
		otbn_illegal_mem_acc	19.000s	47.164us	5	5	100.00
		otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	23.000s	58.835us	10	10	100.00
		otbn_dmem_err	26.000s	65.811us	15	15	100.00
		otbn_zero_state_err_urnd	17.000s	38.583us	5	5	100.00
		otbn_illegal_mem_acc	19.000s	47.164us	5	5	100.00
		otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.250m	27.955us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	23.000s	58.835us	10	10	100.00
		otbn_dmem_err	26.000s	65.811us	15	15	100.00
		otbn_zero_state_err_urnd	17.000s	38.583us	5	5	100.00
		otbn_illegal_mem_acc	19.000s	47.164us	5	5	100.00
		otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	46.754us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	27.000s	55.642us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.050m	642.088us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.050m	642.088us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	11.000s	31.952us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	37.000s	65.649us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	25.000s	61.170us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	25.000s	61.170us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	35.174us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.683m	1.056ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	33.000s	14.266us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	52.000s	802.533us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.133m	6.117ms	5	5	100.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	26.717m	15.513ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			571	585	97.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.97	99.61	95.44	99.70	93.47	93.04	100.00	98.37	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_ctrl_redun has 1 failures.

0.otbn_ctrl_redun.54454244050061135281072111517975362346382497646639017591698945076709003185149
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 8142952 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 8142952 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   8142952 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   8142952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 3 failures.

3.otbn_sec_wipe_err.87785422167308128186896635191659062462156994745814277065017278094336350488669
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38315978 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  38315978 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  38315978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.50144333455680926226532397227691378872805742008823880942510259734244416505759
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35174313 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35174313 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  35174313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_escalate has 1 failures.

53.otbn_escalate.7515229641263586938736947568743818401742829149028313497799511909479578889539
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13092627 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13092627 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  13092627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 2.otbn_stress_all_with_rand_reset.28526904450746657486498699169803460534313211028125165213683355072394114706916
    Line 345, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6305256692 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6305256692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stress_all_with_rand_reset.69863005124444612320449114728103530190273941364838238846572369829673498869964
    Line 953, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11311979229 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 11311979229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:

Test otbn_partial_wipe has 2 failures.

7.otbn_partial_wipe.14376908978062142524851823668892842129687848660232909588892150734247503937069
Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 3235455 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3235455 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3235455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_partial_wipe.104567600631867346258877613090727361371062875072705854926264383010456895596295
Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 3288550 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   3288550 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   3288550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.23214916397708564611025693743295595467333930376395405433006559350982584309745
    Line 411, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 295088281 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 295088281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.64559944633038370834761890368926887627484363627026169988962312735210642140880
    Line 862, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15512997835 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 15512997835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job otbn-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.109099704074862142465398749637861737919279567190860455643471405809680238325132
    Log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c9f97287-1262-4840-b4fa-b18e8fc92567
```
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all has 1 failures.
  - 9.otbn_stress_all.33721647886452889786998830345533469526449463284499248315233163899350952159943
    Line 425, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all/latest/run.log
```
  UVM_FATAL @ 12247160232 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 12247160232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```