OTBN Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	77.405us	1	1	100.00
V1	single_binary	otbn_single	2.083m	1.063ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	45.901us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	14.195us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	142.338us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	18.483us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	29.039us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	14.195us	20	20	100.00
		otbn_csr_aliasing	9.000s	18.483us	5	5	100.00
V1	mem_walk	otbn_mem_walk	47.000s	1.251ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	26.000s	134.933us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	32.000s	154.367us	10	10	100.00
V2	multi_error	otbn_multi_err	50.000s	212.179us	1	1	100.00
V2	back_to_back	otbn_multi	1.583m	405.011us	10	10	100.00
V2	stress_all	otbn_stress_all	2.033m	1.013ms	10	10	100.00
V2	lc_escalation	otbn_escalate	21.000s	58.361us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	62.993us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	24.000s	234.088us	10	10	100.00
V2	alert_test	otbn_alert_test	20.000s	24.213us	50	50	100.00
V2	intr_test	otbn_intr_test	15.000s	18.005us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	196.447us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	196.447us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	45.901us	5	5	100.00
		otbn_csr_rw	10.000s	14.195us	20	20	100.00
		otbn_csr_aliasing	9.000s	18.483us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	16.431us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	45.901us	5	5	100.00
		otbn_csr_rw	10.000s	14.195us	20	20	100.00
		otbn_csr_aliasing	9.000s	18.483us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	16.431us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	11.000s	134.120us	10	10	100.00
		otbn_dmem_err	13.000s	33.928us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	128.915us	5	5	100.00
		otbn_controller_ispr_rdata_err	18.000s	141.113us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	65.168us	5	5	100.00
		otbn_urnd_err	6.000s	15.457us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	29.531us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	38.072us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	14.000s	50.635us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
		otbn_tl_intg_err	43.000s	286.919us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	39.000s	255.325us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	77.405us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	33.928us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	134.120us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	43.000s	286.919us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	21.000s	58.361us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	134.120us	10	10	100.00
		otbn_dmem_err	13.000s	33.928us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	62.993us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	29.531us	5	5	100.00
		otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	134.120us	10	10	100.00
		otbn_dmem_err	13.000s	33.928us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	62.993us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	29.531us	5	5	100.00
		otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	21.000s	58.361us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	134.120us	10	10	100.00
		otbn_dmem_err	13.000s	33.928us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	62.993us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	29.531us	5	5	100.00
		otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	705.926us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	35.326us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.900m	1.230ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.900m	1.230ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	39.733us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	229.446us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	91.284us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	91.284us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	12.815us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.583m	405.011us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	46.000s	257.271us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.083m	1.063ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.467m	6.240ms	5	5	100.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	24.967m	5.556ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			575	585	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.94	99.61	95.49	99.71	93.58	92.33	100.00	98.48	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 1.otbn_stress_all_with_rand_reset.92127709059643862948833483998913476342552456723464966512696685803273771846646
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1706029002 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1706029002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otbn_stress_all_with_rand_reset.32717140219945049938280246729485742782506567071762265501015590652123014834254
    Line 436, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5555680157 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5555680157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 2 failures:

Test otbn_sec_wipe_err has 2 failures.

0.otbn_sec_wipe_err.88756418343779801485133582135196225843237088554770950413839139742788425579766
Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 12815106 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  12815106 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  12815106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.90826650507515245147454982891311546267178535974771240727209333176947473287996
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 33481326 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  33481326 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  33481326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 2.otbn_partial_wipe.66784700666978323761905868018640138766030694073981764126517897852893726839859
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 7322258 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   7322258 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   7322258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 6.otbn_partial_wipe.36073630745620845928970872088711386446299624285709989998317074826451581344468
    Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 25801759 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  25801759 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  25801759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.671447323510302644833806019818026330799987810431649677398524469042842686550
    Line 330, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  21794594 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  21794594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.11904601375900882295135537970608819177955015962874457545193256668392895549553
    Line 386, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1582885792 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1582885792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 55.otbn_escalate.94757886864663501336077317888721906029913720721210862277871603357819298744870
    Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/55.otbn_escalate/latest/run.log
```
  UVM_ERROR @   1231880 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   1231880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```