OTBN Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	164.553us	1	1	100.00
V1	single_binary	otbn_single	1.500m	376.197us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	15.000s	35.629us	5	5	100.00
V1	csr_rw	otbn_csr_rw	12.000s	25.984us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	37.087us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	233.900us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	17.000s	125.174us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	12.000s	25.984us	20	20	100.00
		otbn_csr_aliasing	5.000s	233.900us	5	5	100.00
V1	mem_walk	otbn_mem_walk	50.000s	5.513ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	26.000s	3.992ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	36.000s	83.986us	10	10	100.00
V2	multi_error	otbn_multi_err	46.000s	1.060ms	1	1	100.00
V2	back_to_back	otbn_multi	2.267m	535.719us	10	10	100.00
V2	stress_all	otbn_stress_all	1.500m	1.076ms	10	10	100.00
V2	lc_escalation	otbn_escalate	35.000s	125.973us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	28.706us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	15.000s	28.726us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	292.245us	50	50	100.00
V2	intr_test	otbn_intr_test	21.000s	17.916us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	16.000s	187.827us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	16.000s	187.827us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	15.000s	35.629us	5	5	100.00
		otbn_csr_rw	12.000s	25.984us	20	20	100.00
		otbn_csr_aliasing	5.000s	233.900us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	29.405us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	15.000s	35.629us	5	5	100.00
		otbn_csr_rw	12.000s	25.984us	20	20	100.00
		otbn_csr_aliasing	5.000s	233.900us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	29.405us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	11.000s	19.030us	10	10	100.00
		otbn_dmem_err	13.000s	30.393us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	70.632us	5	5	100.00
		otbn_controller_ispr_rdata_err	9.000s	97.517us	5	5	100.00
		otbn_mac_bignum_acc_err	29.000s	95.788us	5	5	100.00
		otbn_urnd_err	7.000s	10.335us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	23.606us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	31.512us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	27.583us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
		otbn_tl_intg_err	1.650m	697.406us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.167m	400.483us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	164.553us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	30.393us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	11.000s	19.030us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.650m	697.406us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	35.000s	125.973us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	11.000s	19.030us	10	10	100.00
		otbn_dmem_err	13.000s	30.393us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.706us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	23.606us	5	5	100.00
		otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	11.000s	19.030us	10	10	100.00
		otbn_dmem_err	13.000s	30.393us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.706us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	23.606us	5	5	100.00
		otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	35.000s	125.973us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	11.000s	19.030us	10	10	100.00
		otbn_dmem_err	13.000s	30.393us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	28.706us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	23.606us	5	5	100.00
		otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	24.196us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	239.669us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	32.000s	137.558us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	32.000s	137.558us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	20.812us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	222.261us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	44.365us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	44.365us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	20.000s	232.862us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.267m	535.719us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	90.409us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.500m	376.197us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.050m	12.511ms	5	5	100.00
V2S		TOTAL			160	163	98.16
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.833m	6.991ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			576	585	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.93	99.60	95.40	99.70	93.52	92.39	100.00	98.37	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 1 failures.

1.otbn_sec_wipe_err.31536490686306012516937244723385674144176625579301921831376395204701449486002
Line 285, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 232862456 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 232862456 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 232862456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

13.otbn_escalate.82238032131470051184245165479948396459273174727965975551562253987092126604300
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 46784115 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  46784115 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  46784115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.otbn_escalate.44400228515141381686551704329292359513898544587643651816303107880690742600534
Line 296, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/20.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 24848173 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  24848173 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  24848173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 2 failures:
- Test otbn_partial_wipe has 1 failures.
  - 0.otbn_partial_wipe.14542655303822283338472448342095427780794215827764755155642393482681784976540
    Line 280, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 9519346 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   9519346 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   9519346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otbn_sec_wipe_err has 1 failures.
  - 2.otbn_sec_wipe_err.7501377004112000906910183318340956214799727725928452944143104748027025303077
    Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 20103499 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  20103499 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  20103499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.36585894360601411072427745834343857730840933723748694939449178664956503216559
    Line 481, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2088565880 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2088565880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 8.otbn_stress_all_with_rand_reset.61760153468230101001744436591559570333904940527011599634324287232213891428914
    Line 322, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   2484364 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   2484364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 22.otbn_escalate.40876283578503995641854375631673885644041465906276712517739716685420868417558
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/22.otbn_escalate/latest/run.log
```
  UVM_FATAL @  47538705 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @  47538705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 53.otbn_escalate.114657490510294723990025962722463500259073694416980851654606035304438242721526
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/53.otbn_escalate/latest/run.log
```
  UVM_ERROR @   1541417 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   1541417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```