OTBN Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	81.475us	1	1	100.00
V1	single_binary	otbn_single	2.783m	683.115us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	28.335us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	17.040us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	145.296us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	54.290us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	41.130us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	17.040us	20	20	100.00
		otbn_csr_aliasing	5.000s	54.290us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.000m	2.014ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	26.000s	596.540us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.017m	366.171us	10	10	100.00
V2	multi_error	otbn_multi_err	44.000s	770.980us	1	1	100.00
V2	back_to_back	otbn_multi	2.800m	711.925us	10	10	100.00
V2	stress_all	otbn_stress_all	2.083m	500.085us	10	10	100.00
V2	lc_escalation	otbn_escalate	42.000s	169.440us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	86.978us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	58.000s	170.839us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	20.707us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	33.050us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	15.000s	55.385us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	15.000s	55.385us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	28.335us	5	5	100.00
		otbn_csr_rw	6.000s	17.040us	20	20	100.00
		otbn_csr_aliasing	5.000s	54.290us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	29.759us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	28.335us	5	5	100.00
		otbn_csr_rw	6.000s	17.040us	20	20	100.00
		otbn_csr_aliasing	5.000s	54.290us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	29.759us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	17.000s	64.567us	10	10	100.00
		otbn_dmem_err	12.000s	36.849us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	60.393us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	214.429us	5	5	100.00
		otbn_mac_bignum_acc_err	16.000s	443.238us	5	5	100.00
		otbn_urnd_err	7.000s	19.804us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	24.077us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	171.554us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	375.515us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
		otbn_tl_intg_err	37.000s	449.343us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.083m	364.919us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	prim_count_check	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	81.475us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	36.849us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	64.567us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	37.000s	449.343us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	42.000s	169.440us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	64.567us	10	10	100.00
		otbn_dmem_err	12.000s	36.849us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	86.978us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	24.077us	5	5	100.00
		otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	64.567us	10	10	100.00
		otbn_dmem_err	12.000s	36.849us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	86.978us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	24.077us	5	5	100.00
		otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	42.000s	169.440us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	64.567us	10	10	100.00
		otbn_dmem_err	12.000s	36.849us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	86.978us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	24.077us	5	5	100.00
		otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	50.962us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	16.000s	53.417us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.800m	6.887ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.800m	6.887ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	18.895us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	70.603us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.400m	280.437us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.400m	280.437us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	11.000s	50.996us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.800m	711.925us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	30.000s	114.226us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.783m	683.115us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.567m	1.897ms	5	5	100.00
V2S		TOTAL			161	163	98.77
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	13.033m	3.664ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			578	585	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.96	99.60	95.40	99.69	93.55	92.79	100.00	98.60	99.16

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test otbn_stress_all_with_rand_reset has 2 failures.

    • 2.otbn_stress_all_with_rand_reset.24701980332929721793712639194567947472902003029837985096016202640006849402038
      Line 355, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1683604040 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1683604040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.otbn_stress_all_with_rand_reset.70641958740199499205078789803755204851549532959185696284311685842507469526537
      Line 800, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2457023652 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2457023652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Exit reason: Error: User command failed UVM_FATAL (otbn_base_vseq.sv:486) [otbn_single_vseq] Timed out waiting for OTBN run to complete has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 4.otbn_stress_all_with_rand_reset.39794634429750990809122434769660577989977239976484766647142691874822296176964
      Line 413, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 11015200372 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete
        UVM_INFO @ 11015200372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 4.otbn_sec_wipe_err.109747727203018350403712609204204624490194788198753579853886630934621473156918
      Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 50995710 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  50995710 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  50995710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 4.otbn_partial_wipe.26492007705119631386756851473266767354728789378736485077639042386774895945071
      Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 12699518 PS) Assertion tb.dut.NotBusyAndDone_A has failed
        UVM_ERROR @  12699518 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
        UVM_INFO @  12699518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 5.otbn_stress_all_with_rand_reset.91736121103240553650208061455146122771710935827763470246885009504637810234504
      Line 389, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3663935015 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 3663935015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:

  • Test otbn_escalate has 1 failures.

    • 33.otbn_escalate.18331565031898779502971029466814494684315839088958845322019747308854768788433
      Line 283, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/33.otbn_escalate/latest/run.log

        UVM_ERROR @   2854417 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
        UVM_INFO @   2854417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.07.21_08.26.47
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