OTBN Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	534.662us	1	1	100.00
V1	single_binary	otbn_single	39.000s	97.614us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	21.043us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	22.444us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	883.457us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	15.376us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	63.367us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	22.444us	20	20	100.00
		otbn_csr_aliasing	5.000s	15.376us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	8.501ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	1.090ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	47.000s	165.444us	10	10	100.00
V2	multi_error	otbn_multi_err	49.000s	162.098us	1	1	100.00
V2	back_to_back	otbn_multi	2.417m	275.476us	10	10	100.00
V2	stress_all	otbn_stress_all	2.050m	434.383us	10	10	100.00
V2	lc_escalation	otbn_escalate	2.950m	2.928ms	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	46.337us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	56.000s	205.432us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	86.777us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	14.082us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	839.853us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	839.853us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	21.043us	5	5	100.00
		otbn_csr_rw	8.000s	22.444us	20	20	100.00
		otbn_csr_aliasing	5.000s	15.376us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	22.362us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	21.043us	5	5	100.00
		otbn_csr_rw	8.000s	22.444us	20	20	100.00
		otbn_csr_aliasing	5.000s	15.376us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	22.362us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	42.000s	171.093us	10	10	100.00
		otbn_dmem_err	49.000s	215.737us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	28.000s	395.826us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	167.953us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	143.245us	5	5	100.00
		otbn_urnd_err	6.000s	16.042us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	62.323us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	13.000s	51.430us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	39.434us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
		otbn_tl_intg_err	31.000s	208.332us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	37.000s	199.243us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	534.662us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	49.000s	215.737us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	42.000s	171.093us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	31.000s	208.332us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.950m	2.928ms	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	42.000s	171.093us	10	10	100.00
		otbn_dmem_err	49.000s	215.737us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	46.337us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	62.323us	5	5	100.00
		otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	42.000s	171.093us	10	10	100.00
		otbn_dmem_err	49.000s	215.737us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	46.337us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	62.323us	5	5	100.00
		otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.950m	2.928ms	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	42.000s	171.093us	10	10	100.00
		otbn_dmem_err	49.000s	215.737us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	46.337us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	62.323us	5	5	100.00
		otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	12.000s	83.496us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	37.509us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	2.217m	368.187us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	2.217m	368.187us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	80.880us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	70.882us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	68.325us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	10.000s	68.325us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	35.616us	3	7	42.86
V2S	sec_cm_data_mem_sec_wipe	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.417m	275.476us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	109.113us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	39.000s	97.614us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.250m	6.984ms	1	5	20.00
V2S		TOTAL			155	163	95.09
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	9.250m	2.667ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.59	95.18	99.68	93.44	92.95	97.44	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 4 failures.

0.otbn_sec_wipe_err.58877677661331135059097912139491642166326576683353303360255640780052255553261
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 7924208 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   7924208 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   7924208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_wipe_err.25471581544348125020959785535174767595561080970029664748327275532873109206680
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 51950407 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  51950407 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  51950407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

0.otbn_sec_cm.6278849640932933650708496600623024975951195110842588935909880609994699934373
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 82770835 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 82770835 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 82770835 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 82770835 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 82770835 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.6548076880899629455978350126450530627528862586316297068265910062592998754688
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 60405066 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 60405066 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 60405066 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 60405066 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 60405066 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 3.otbn_stress_all_with_rand_reset.71336934466795257572000961975580539173946276608168686277644548838970009800993
    Line 867, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1545681771 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1545681771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otbn_stress_all_with_rand_reset.9900245845962632135727246013332412859778266310027259023683223740263281906830
    Line 332, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  23536245 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  23536245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 1.otbn_stress_all_with_rand_reset.7076720094160449393951404811974893353797987086076409423709275667563130144734
    Line 460, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2667340112 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2667340112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.93830767127490428590929686284711863635239463007802681005862791105264450608065
    Line 334, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 132133004 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 132133004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 3.otbn_escalate.77413157811691808451558510271630150109643395445492435233432084763953455630565
    Line 294, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_escalate/latest/run.log
```
  UVM_ERROR @  44929934 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (255 [0xff] vs 4 [0x4]) value for register otbn_reg_block.status
  UVM_INFO @  44929934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.41247793013346737919382365039580344956121793771372986373554073922006497285171
    Line 485, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1375269372 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1375269372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```