OTBN Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	62.645us	1	1	100.00
V1	single_binary	otbn_single	1.617m	396.445us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	18.827us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	19.360us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	130.367us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	396.433us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	54.152us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	19.360us	20	20	100.00
		otbn_csr_aliasing	6.000s	396.433us	5	5	100.00
V1	mem_walk	otbn_mem_walk	55.000s	4.786ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	20.000s	355.602us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.117m	332.201us	9	10	90.00
V2	multi_error	otbn_multi_err	1.400m	212.797us	1	1	100.00
V2	back_to_back	otbn_multi	2.783m	648.807us	10	10	100.00
V2	stress_all	otbn_stress_all	1.817m	438.237us	10	10	100.00
V2	lc_escalation	otbn_escalate	46.000s	180.905us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	16.627us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	6.333m	1.474ms	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	32.677us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	32.298us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	14.000s	61.407us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	14.000s	61.407us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	18.827us	5	5	100.00
		otbn_csr_rw	7.000s	19.360us	20	20	100.00
		otbn_csr_aliasing	6.000s	396.433us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	36.157us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	18.827us	5	5	100.00
		otbn_csr_rw	7.000s	19.360us	20	20	100.00
		otbn_csr_aliasing	6.000s	396.433us	5	5	100.00
		otbn_same_csr_outstanding	8.000s	36.157us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	15.000s	52.254us	10	10	100.00
		otbn_dmem_err	12.000s	41.361us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	56.471us	5	5	100.00
		otbn_controller_ispr_rdata_err	14.000s	908.544us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	216.359us	5	5	100.00
		otbn_urnd_err	9.000s	28.822us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	23.116us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	12.861us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	13.000s	70.385us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
		otbn_tl_intg_err	28.000s	187.977us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	46.000s	244.649us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	62.645us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	41.361us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	52.254us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	28.000s	187.977us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	46.000s	180.905us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	52.254us	10	10	100.00
		otbn_dmem_err	12.000s	41.361us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.627us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	23.116us	5	5	100.00
		otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	52.254us	10	10	100.00
		otbn_dmem_err	12.000s	41.361us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.627us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	23.116us	5	5	100.00
		otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	46.000s	180.905us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	52.254us	10	10	100.00
		otbn_dmem_err	12.000s	41.361us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.627us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	23.116us	5	5	100.00
		otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	23.000s	175.936us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	131.909us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	46.000s	155.096us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	46.000s	155.096us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	69.867us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	62.679us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	38.531us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	38.531us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	17.000s	25.505us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.783m	648.807us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	92.079us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.617m	396.445us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.050m	1.891ms	2	5	40.00
V2S		TOTAL			159	163	97.55
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	25.100m	5.220ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			578	585	98.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.92	99.61	95.53	99.69	93.49	92.94	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.85044023572835157909559878319412605856187851095424008357495322842168989494355
Line 355, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 364815622 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 364815622 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 364815622 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 364815622 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 364815622 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.103042107676094302067771835586740446099651423385771746811452332029796621673015
Line 330, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 162207954 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 162207954 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 162207954 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 162207954 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 162207954 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:840) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.106631542020445484413881113494050054122314218850164174692926790916071897151763
    Line 588, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5220045799 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5220045799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 2.otbn_sec_wipe_err.90947239495797986602425811485149373464592853066578161273279346753972715204000
    Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25505210 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  25505210 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  25505210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 7.otbn_stress_all_with_rand_reset.27664570986893841273437815620833862661524352465251794866698666727443827584280
    Line 319, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  31473074 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  31473074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_reset has 1 failures.
  - 9.otbn_reset.101387664214504409481093009745470846045736907110549399599553337492209453068342
    Line 309, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/9.otbn_reset/latest/run.log
```
  UVM_FATAL @ 205977177 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @ 205977177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```