OTBN Simulation Results

Monday July 29 2024 23:02:32 UTC

GitHub Revision: `39f3866b56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 91682663165753342493852681547271085771042321116470426223748766059309541455602

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	133.499us	1	1	100.00
V1	single_binary	otbn_single	55.000s	411.719us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	22.564us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	17.298us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	277.166us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	17.067us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	57.861us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	17.298us	20	20	100.00
		otbn_csr_aliasing	6.000s	17.067us	5	5	100.00
V1	mem_walk	otbn_mem_walk	27.000s	2.394ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	19.000s	1.646ms	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	1.850m	427.418us	10	10	100.00
V2	multi_error	otbn_multi_err	51.000s	487.199us	1	1	100.00
V2	back_to_back	otbn_multi	2.233m	341.380us	10	10	100.00
V2	stress_all	otbn_stress_all	7.067m	1.988ms	10	10	100.00
V2	lc_escalation	otbn_escalate	25.000s	74.633us	56	60	93.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	26.295us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	27.000s	77.143us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	40.929us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	17.268us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	11.000s	113.311us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	11.000s	113.311us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	22.564us	5	5	100.00
		otbn_csr_rw	6.000s	17.298us	20	20	100.00
		otbn_csr_aliasing	6.000s	17.067us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	101.267us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	22.564us	5	5	100.00
		otbn_csr_rw	6.000s	17.298us	20	20	100.00
		otbn_csr_aliasing	6.000s	17.067us	5	5	100.00
		otbn_same_csr_outstanding	6.000s	101.267us	20	20	100.00
V2		TOTAL			242	246	98.37
V2S	mem_integrity	otbn_imem_err	12.000s	25.700us	10	10	100.00
		otbn_dmem_err	31.000s	120.747us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	32.000s	110.107us	5	5	100.00
		otbn_controller_ispr_rdata_err	12.000s	114.101us	5	5	100.00
		otbn_mac_bignum_acc_err	6.050m	1.504ms	5	5	100.00
		otbn_urnd_err	7.000s	16.217us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	24.131us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	19.708us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	58.405us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
		otbn_tl_intg_err	55.000s	347.444us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	40.000s	233.663us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	133.499us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	31.000s	120.747us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	25.700us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	55.000s	347.444us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	25.000s	74.633us	56	60	93.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	25.700us	10	10	100.00
		otbn_dmem_err	31.000s	120.747us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	26.295us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.131us	5	5	100.00
		otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.700us	10	10	100.00
		otbn_dmem_err	31.000s	120.747us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	26.295us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.131us	5	5	100.00
		otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	25.000s	74.633us	56	60	93.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.700us	10	10	100.00
		otbn_dmem_err	31.000s	120.747us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	26.295us	5	5	100.00
		otbn_illegal_mem_acc	9.000s	24.131us	5	5	100.00
		otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	276.060us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	21.441us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.083m	587.462us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.083m	587.462us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	52.289us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	18.000s	111.052us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	50.381us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	50.381us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	18.000s	129.749us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.233m	341.380us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	78.299us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	55.000s	411.719us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.633m	1.823ms	1	5	20.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.324h	46.726ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.92	99.61	95.53	99.70	93.47	93.03	97.44	91.61	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

0.otbn_sec_cm.90945888449136917719088533290374335222949489739082492373838924597469365925378
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 31102897 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 31102897 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 31102897 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 31102897 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 31102897 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.104207188511250249636379492977714516663478694848296026146904505623541656644905
Line 320, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 282285921 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 282285921 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 282285921 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 282285921 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 282285921 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_escalate has 3 failures.

2.otbn_escalate.10258004795114669131576900918609832206967914866346125533814031844142914146537
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60899309 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  60899309 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  60899309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.otbn_escalate.12795011534787115107728817669589056512951326126015894903460395952349362690593
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 171802827 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 171802827 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 171802827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 0.otbn_rf_base_intg_err.104064419513565987753445935943361006880911282331521738817211427096134249084736
    Line 291, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_rf_base_intg_err/latest/run.log
```
  UVM_ERROR @  13838547 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_otbn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  13838547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 0.otbn_stress_all_with_rand_reset.71217824647360877063486482474251099228915967686116120701288374236570845602945
    Line 441, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 9696317664 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 9696317664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.104085612669837620350679726976268889539328510163905357364570808741822685830404
    Line 624, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1708349672 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1708349672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 4.otbn_partial_wipe.80889072511726685033975669256475283247658692189195556964294812411457337778946
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 7238396 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   7238396 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   7238396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.102073401638201395468590392253349722458949948135226490545470783455562850706918
    Line 862, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 46726193991 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 46726193991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 7.otbn_partial_wipe.7524721091814185035602008842912139522468220860541951067056008688152719069532
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 15154085 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  15154085 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  15154085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 51.otbn_escalate.2639728361377063565069512186830871262324323940970066967408741206828893688125
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/51.otbn_escalate/latest/run.log
```
  UVM_ERROR @   5889190 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5889190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 58.otbn_single.76415776922849704604559773266826304048520380060607685754597644411972503918079
    Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/58.otbn_single/latest/run.log
```
  UVM_FATAL @  31339054 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  31339054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```