OTBN Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	39.881us	1	1	100.00
V1	single_binary	otbn_single	1.000m	1.301ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	24.793us	5	5	100.00
V1	csr_rw	otbn_csr_rw	10.000s	17.257us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	187.299us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	30.534us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	39.244us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	10.000s	17.257us	20	20	100.00
		otbn_csr_aliasing	5.000s	30.534us	5	5	100.00
V1	mem_walk	otbn_mem_walk	50.000s	1.203ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	21.000s	266.363us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	41.000s	164.971us	10	10	100.00
V2	multi_error	otbn_multi_err	48.000s	345.819us	1	1	100.00
V2	back_to_back	otbn_multi	4.867m	1.356ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.500m	341.167us	10	10	100.00
V2	lc_escalation	otbn_escalate	19.000s	185.019us	53	60	88.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	29.593us	4	5	80.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	27.000s	66.693us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	46.411us	50	50	100.00
V2	intr_test	otbn_intr_test	6.000s	23.321us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	16.000s	212.762us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	16.000s	212.762us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	24.793us	5	5	100.00
		otbn_csr_rw	10.000s	17.257us	20	20	100.00
		otbn_csr_aliasing	5.000s	30.534us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	73.685us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	24.793us	5	5	100.00
		otbn_csr_rw	10.000s	17.257us	20	20	100.00
		otbn_csr_aliasing	5.000s	30.534us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	73.685us	20	20	100.00
V2		TOTAL			238	246	96.75
V2S	mem_integrity	otbn_imem_err	17.000s	66.510us	10	10	100.00
		otbn_dmem_err	17.000s	124.264us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	227.868us	5	5	100.00
		otbn_controller_ispr_rdata_err	9.000s	144.186us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	81.980us	5	5	100.00
		otbn_urnd_err	9.000s	20.295us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	24.905us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	7.000s	44.544us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	31.760us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
		otbn_tl_intg_err	25.000s	262.044us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	57.000s	328.782us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	39.881us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	17.000s	124.264us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	66.510us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	25.000s	262.044us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	19.000s	185.019us	53	60	88.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	66.510us	10	10	100.00
		otbn_dmem_err	17.000s	124.264us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	29.593us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	24.905us	5	5	100.00
		otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	66.510us	10	10	100.00
		otbn_dmem_err	17.000s	124.264us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	29.593us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	24.905us	5	5	100.00
		otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	19.000s	185.019us	53	60	88.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	66.510us	10	10	100.00
		otbn_dmem_err	17.000s	124.264us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	29.593us	4	5	80.00
		otbn_illegal_mem_acc	9.000s	24.905us	5	5	100.00
		otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	42.756us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	22.850us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.517m	447.871us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.517m	447.871us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	54.024us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	12.000s	65.220us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	44.000s	318.484us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	44.000s	318.484us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	18.000s	57.222us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.867m	1.356ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	16.276us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.000m	1.301ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.283m	3.984ms	4	5	80.00
V2S		TOTAL			162	163	99.39
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.450h	122.195ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			572	585	97.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	9	81.82
V2S	20	20	19	95.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.99	99.62	95.62	99.70	93.58	93.09	100.00	98.60	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_zero_state_err_urnd has 1 failures.

0.otbn_zero_state_err_urnd.99347293059624698791233365386224770488520877937269829085417280085464980061033
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_zero_state_err_urnd/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 51801214 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  51801214 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  51801214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 5 failures.

6.otbn_escalate.28084905871885327880122393511767413379318637194888748181957025355655409846260
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 70683914 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  70683914 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  70683914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.otbn_escalate.74708431485555542964950325837401805652401394236355263888430293175126968501398
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/10.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 236744500 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 236744500 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 236744500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.91717705867929630439868283313026239835141464223049749693781832131936949640711
    Line 397, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6240121363 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6240121363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otbn_stress_all_with_rand_reset.42978548862900584198892157891293773111581802347300006811964895200758169481591
    Line 354, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2365068410 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2365068410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 2 failures:

Test otbn_escalate has 2 failures.

44.otbn_escalate.51754186646050233761358377235155994845867108281732180312183624086642471208221
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/44.otbn_escalate/latest/run.log

  UVM_ERROR @   3595534 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   3595534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.otbn_escalate.105081696912591155247860365052877832731416828776540203433338358612778774363602
Line 281, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/48.otbn_escalate/latest/run.log

  UVM_ERROR @   4385170 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   4385170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

1.otbn_sec_cm.97573613995356867933296426593896467014168781424942954536804706182625944386359
Line 340, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 1088260208 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 1088260208 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 1088260208 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 1088260208 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 1088260208 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.113739939010436874540781110671722313690394856450593364785510239214746556523474
    Line 977, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 122194869157 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 122194869157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_single_vseq] Timed out waiting for OTBN run to complete has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.90397775459826265250588888437654121382865778798532282590779237295930922467780
    Line 374, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10170575584 ps: (otbn_base_vseq.sv:486) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Timed out waiting for OTBN run to complete
  UVM_INFO @ 10170575584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```