OTBN Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	326.996us	1	1	100.00
V1	single_binary	otbn_single	1.050m	285.274us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	17.441us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	22.109us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	139.725us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	21.846us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	14.000s	44.133us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	22.109us	20	20	100.00
		otbn_csr_aliasing	6.000s	21.846us	5	5	100.00
V1	mem_walk	otbn_mem_walk	56.000s	1.789ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	17.000s	3.612ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	46.000s	165.307us	10	10	100.00
V2	multi_error	otbn_multi_err	1.133m	1.092ms	1	1	100.00
V2	back_to_back	otbn_multi	6.867m	16.158ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.533m	356.797us	10	10	100.00
V2	lc_escalation	otbn_escalate	2.200m	574.669us	52	60	86.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	58.040us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	69.981us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	20.656us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	33.165us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	171.191us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	171.191us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	17.441us	5	5	100.00
		otbn_csr_rw	7.000s	22.109us	20	20	100.00
		otbn_csr_aliasing	6.000s	21.846us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	29.001us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	17.441us	5	5	100.00
		otbn_csr_rw	7.000s	22.109us	20	20	100.00
		otbn_csr_aliasing	6.000s	21.846us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	29.001us	20	20	100.00
V2		TOTAL			238	246	96.75
V2S	mem_integrity	otbn_imem_err	21.000s	89.512us	10	10	100.00
		otbn_dmem_err	13.000s	228.602us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	53.000s	882.307us	5	5	100.00
		otbn_controller_ispr_rdata_err	11.000s	109.078us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	62.581us	5	5	100.00
		otbn_urnd_err	7.000s	43.001us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	40.365us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	21.171us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	26.482us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
		otbn_tl_intg_err	46.000s	326.151us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	444.246us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	326.996us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	13.000s	228.602us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	21.000s	89.512us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	46.000s	326.151us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.200m	574.669us	52	60	86.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	21.000s	89.512us	10	10	100.00
		otbn_dmem_err	13.000s	228.602us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	58.040us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	40.365us	5	5	100.00
		otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	21.000s	89.512us	10	10	100.00
		otbn_dmem_err	13.000s	228.602us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	58.040us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	40.365us	5	5	100.00
		otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.200m	574.669us	52	60	86.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	21.000s	89.512us	10	10	100.00
		otbn_dmem_err	13.000s	228.602us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	58.040us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	40.365us	5	5	100.00
		otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	11.000s	32.528us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	14.000s	52.804us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	58.000s	260.330us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	58.000s	260.330us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	19.649us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	2.150m	490.736us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	132.861us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	132.861us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	14.000s	67.909us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	6.867m	16.158ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	27.000s	409.597us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.050m	285.274us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	7.483m	7.811ms	1	5	20.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.526h	35.708ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			566	585	96.75

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.86	99.60	95.31	99.69	93.52	92.29	97.44	91.38	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 7 failures:

Test otbn_escalate has 7 failures.

2.otbn_escalate.101140272965861984413471864728680648932234673412274486682796352255675313429587
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 33294569 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  33294569 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  33294569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_escalate.2348738747102217691095454012341621474960250262919782563531165484364226227446
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 10304135 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  10304135 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  10304135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

0.otbn_sec_cm.92310648651711844803334467199939178840093818343053110373041957257961923248782
Line 335, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 371565487 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 371565487 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 371565487 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 371565487 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 371565487 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.104496247912770246575732126311291526130062984347741961525848730292419617341998
Line 289, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 161379916 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 161379916 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 161379916 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 161379916 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 161379916 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 1.otbn_stress_all_with_rand_reset.93100968671903412060841524678235739399223045858086863476314897813610325150125
    Line 681, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6507501444 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6507501444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otbn_stress_all_with_rand_reset.60132555148301675474267682152449244181505876982921526888408922227022851888018
    Line 786, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10024876765 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10024876765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 1.otbn_partial_wipe.40989975072958051094921926167743170565457514603063299534207130232446918069868
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 6466596 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   6466596 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   6466596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 2.otbn_stress_all_with_rand_reset.27976637033309604208410000462249812374452735406903731312789844998513583097746
    Line 531, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35707963999 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 35707963999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_ctrl_redun_vseq.sv:24) virtual_sequencer [otbn_ctrl_redun_vseq] Never found a time to inject an error. has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 7.otbn_ctrl_redun.75911913083606586213729389106703593118905858123261298343314827769336256560966
    Line 300, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_ctrl_redun/latest/run.log
```
  UVM_FATAL @  15141909 ps: (otbn_ctrl_redun_vseq.sv:24) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otbn_ctrl_redun_vseq] Never found a time to inject an error.
  UVM_INFO @  15141909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 8.otbn_partial_wipe.24928621543769816744096299448658895882541159839950966904377840531258401162104
    Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 6839335 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6839335 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6839335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 16.otbn_escalate.29395986772679410739617888533857602964658109666187418069411597468517429367662
    Line 282, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/16.otbn_escalate/latest/run.log
```
  UVM_ERROR @   9961481 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   9961481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```