OTBN Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	135.236us	1	1	100.00
V1	single_binary	otbn_single	1.283m	323.126us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	49.684us	5	5	100.00
V1	csr_rw	otbn_csr_rw	6.000s	13.535us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	374.132us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	85.780us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	16.000s	90.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	13.535us	20	20	100.00
		otbn_csr_aliasing	6.000s	85.780us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.017m	7.770ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	23.000s	410.802us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	52.000s	205.980us	10	10	100.00
V2	multi_error	otbn_multi_err	1.817m	284.668us	1	1	100.00
V2	back_to_back	otbn_multi	3.300m	790.503us	10	10	100.00
V2	stress_all	otbn_stress_all	7.700m	2.015ms	10	10	100.00
V2	lc_escalation	otbn_escalate	20.000s	63.628us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	14.860us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	26.000s	833.182us	10	10	100.00
V2	alert_test	otbn_alert_test	7.000s	19.521us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	93.133us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	9.000s	43.294us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	9.000s	43.294us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	49.684us	5	5	100.00
		otbn_csr_rw	6.000s	13.535us	20	20	100.00
		otbn_csr_aliasing	6.000s	85.780us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	62.747us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	49.684us	5	5	100.00
		otbn_csr_rw	6.000s	13.535us	20	20	100.00
		otbn_csr_aliasing	6.000s	85.780us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	62.747us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	20.000s	77.025us	10	10	100.00
		otbn_dmem_err	15.000s	40.809us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	24.000s	46.565us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	72.807us	5	5	100.00
		otbn_mac_bignum_acc_err	13.000s	31.340us	5	5	100.00
		otbn_urnd_err	8.000s	56.855us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	66.878us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	25.845us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	28.707us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
		otbn_tl_intg_err	23.000s	181.441us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	38.000s	206.979us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	135.236us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	40.809us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	20.000s	77.025us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	23.000s	181.441us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	20.000s	63.628us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	20.000s	77.025us	10	10	100.00
		otbn_dmem_err	15.000s	40.809us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	14.860us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	66.878us	5	5	100.00
		otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	20.000s	77.025us	10	10	100.00
		otbn_dmem_err	15.000s	40.809us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	14.860us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	66.878us	5	5	100.00
		otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	20.000s	63.628us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	20.000s	77.025us	10	10	100.00
		otbn_dmem_err	15.000s	40.809us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	14.860us	5	5	100.00
		otbn_illegal_mem_acc	8.000s	66.878us	5	5	100.00
		otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	26.070us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	9.000s	14.718us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	42.000s	136.128us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	42.000s	136.128us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	15.000s	42.070us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	18.000s	124.538us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	86.749us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	17.000s	86.749us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	52.000s	342.751us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.300m	790.503us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	14.000s	72.632us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.283m	323.126us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.750m	4.153ms	2	5	40.00
V2S		TOTAL			154	163	94.48
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	14.533m	8.015ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			571	585	97.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	14	70.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.94	99.61	95.49	99.70	93.49	92.43	100.00	98.83	99.16

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_ctrl_redun has 1 failures.

3.otbn_ctrl_redun.10170346831865043420543891735832446592361224782599095502669856181080122682333
Line 290, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/3.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 29180844 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 29180844 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  29180844 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  29180844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stack_addr_integ_chk has 1 failures.

4.otbn_stack_addr_integ_chk.107444966058038331984826049248700880645198956654727011667413886261926035088253
Line 295, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/4.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 7164345 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 7164345 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   7164345 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   7164345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 3 failures.

15.otbn_escalate.1058343078167451199901965673727197852052562466502707427432645782616143403116
Line 288, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/15.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35932428 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  35932428 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  35932428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.otbn_escalate.10659883638461334912449520678298308306028380739238331049443903027296648520808
Line 293, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/29.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23648149 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  23648149 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  23648149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,884): Assertion NotBusyAndDone_A has failed has 3 failures:

Test otbn_partial_wipe has 2 failures.

0.otbn_partial_wipe.36148715172055498410744582560742869000564521939078807702422958753054929714495
Line 284, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 10590159 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  10590159 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  10590159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.otbn_partial_wipe.62493372727750604047863417690428664236010013965951636134379866656978682724285
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 8226995 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @   8226995 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @   8226995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 1 failures.

6.otbn_sec_wipe_err.63674410163890925313197167346169655662134488760997998843459468151540821097278
Line 286, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,884): (time 15926492 PS) Assertion tb.dut.NotBusyAndDone_A has failed
  UVM_ERROR @  15926492 ps: (otbn.sv:884) [ASSERT FAILED] NotBusyAndDone_A
  UVM_INFO @  15926492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1381): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.31197136065639226779408087469228522519984820579029474407829094681708912147574
Line 305, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 223836251 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 223836251 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 223836251 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 223836251 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 223836251 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.96123808498285812871913117865984043868657454821868148565934931876652276261551
Line 336, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1381): (time 203051987 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 203051987 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 203051987 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 203051987 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 203051987 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:837) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.12184345677782769131414228420461807933591291856350957297543653044506062233069
    Line 432, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1558877717 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1558877717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.92195853437269067925269387975178378462938061426116542523340003510300062624034
    Line 447, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2996115636 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2996115636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:343) [otbn_rf_base_intg_err_vseq] Check failed (stop_tokens == *) has 1 failures:
- Test otbn_rf_base_intg_err has 1 failures.
  - 7.otbn_rf_base_intg_err.73912536551114994237574959931400161104479534488408429669303930800588211387006
    Line 287, in log /container/opentitan-public/scratch/os_regression/otbn-sim-xcelium/7.otbn_rf_base_intg_err/latest/run.log
```
  UVM_FATAL @  49947849 ps: (otbn_base_vseq.sv:343) [uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq] Check failed (stop_tokens == 0)
  UVM_INFO @  49947849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```