OTBN Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: XCELIUM

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	2.017m	114.301us	1	1	100.00
V1	single_binary	otbn_single	1.983m	522.570us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	2.000m	15.620us	5	5	100.00
V1	csr_rw	otbn_csr_rw	1.150m	14.245us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	1.200m	524.976us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	58.000s	123.582us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	1.067m	300.758us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	1.150m	14.245us	20	20	100.00
		otbn_csr_aliasing	58.000s	123.582us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.833m	6.297ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	1.317m	3.265ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.833m	235.703us	10	10	100.00
V2	multi_error	otbn_multi_err	2.500m	298.287us	1	1	100.00
V2	back_to_back	otbn_multi	2.767m	1.352ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.767m	302.269us	10	10	100.00
V2	lc_escalation	otbn_escalate	2.900m	1.552ms	55	60	91.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	1.867m	31.252us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.467m	15.522us	10	10	100.00
V2	alert_test	otbn_alert_test	1.017m	17.304us	50	50	100.00
V2	intr_test	otbn_intr_test	51.000s	15.741us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	1.267m	123.896us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	1.267m	123.896us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	2.000m	15.620us	5	5	100.00
		otbn_csr_rw	1.150m	14.245us	20	20	100.00
		otbn_csr_aliasing	58.000s	123.582us	5	5	100.00
		otbn_same_csr_outstanding	1.300m	39.659us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	2.000m	15.620us	5	5	100.00
		otbn_csr_rw	1.150m	14.245us	20	20	100.00
		otbn_csr_aliasing	58.000s	123.582us	5	5	100.00
		otbn_same_csr_outstanding	1.300m	39.659us	20	20	100.00
V2		TOTAL			241	246	97.97
V2S	mem_integrity	otbn_imem_err	1.467m	35.324us	10	10	100.00
		otbn_dmem_err	1.850m	13.162us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	3.167m	2.122ms	5	5	100.00
		otbn_controller_ispr_rdata_err	1.083m	115.339us	5	5	100.00
		otbn_mac_bignum_acc_err	2.033m	419.237us	5	5	100.00
		otbn_urnd_err	1.150m	30.222us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	51.000s	68.605us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	1.050m	34.103us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	1.033m	247.916us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
		otbn_tl_intg_err	1.117m	107.211us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.533m	880.916us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	2.017m	114.301us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	1.850m	13.162us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	1.467m	35.324us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.117m	107.211us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.900m	1.552ms	55	60	91.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	1.467m	35.324us	10	10	100.00
		otbn_dmem_err	1.850m	13.162us	15	15	100.00
		otbn_zero_state_err_urnd	1.867m	31.252us	5	5	100.00
		otbn_illegal_mem_acc	51.000s	68.605us	5	5	100.00
		otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	1.467m	35.324us	10	10	100.00
		otbn_dmem_err	1.850m	13.162us	15	15	100.00
		otbn_zero_state_err_urnd	1.867m	31.252us	5	5	100.00
		otbn_illegal_mem_acc	51.000s	68.605us	5	5	100.00
		otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.900m	1.552ms	55	60	91.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	1.467m	35.324us	10	10	100.00
		otbn_dmem_err	1.850m	13.162us	15	15	100.00
		otbn_zero_state_err_urnd	1.867m	31.252us	5	5	100.00
		otbn_illegal_mem_acc	51.000s	68.605us	5	5	100.00
		otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	56.000s	19.777us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	32.000s	13.028us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.700m	120.730us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.700m	120.730us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	57.000s	57.875us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	47.000s	128.826us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.117m	84.206us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.117m	84.206us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	58.000s	84.350us	7	7	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.767m	1.352ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	1.117m	30.516us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.983m	522.570us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.317m	3.972ms	1	5	20.00
V2S		TOTAL			158	163	96.93
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	12.400m	8.048ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			567	585	96.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.95	99.59	95.31	99.69	93.58	92.87	97.44	98.83	98.32

Failure Buckets

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 6 failures:

Test otbn_stack_addr_integ_chk has 1 failures.

0.otbn_stack_addr_integ_chk.111096761848887499999604407603655145585781528106632220058973095324049270637289
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/0.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 84205736 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 84205736 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  84205736 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  84205736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 5 failures.

1.otbn_escalate.4127238384900587518056750341586790777050645319980637368357832874740606621706
Line 98, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/1.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 30527850 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  30527850 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  30527850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.otbn_escalate.75911722588303994554731310502164386196665168930168551843481074618265061597199
Line 96, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/27.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 160827318 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 160827318 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 160827318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 0.otbn_stress_all_with_rand_reset.95237199233246296065552730603130841971468993475906948026166512756848961347229
    Line 199, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1015911663 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1015911663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.otbn_stress_all_with_rand_reset.2962163733984012515863939806808666016588408095976553560571000539169812699826
    Line 166, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 329831629 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 329831629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

1.otbn_sec_cm.47512956690067414417427236603125111666616853809666649179821628146150397693675
Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 92623586 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 92623586 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 92623586 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 92623586 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 92623586 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

2.otbn_sec_cm.4235661078810414344171575618441404886268733574646780556267580606042243047173
Line 85, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 22739208 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 22739208 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 22739208 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 22739208 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 22739208 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 5.otbn_stress_all_with_rand_reset.5458537408887225167771049085861030381244195245862414383659596980054416211917
    Line 490, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2595363387 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2595363387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otbn_stress_all_with_rand_reset.87639020823305777591009017242666163697806892227642980352645927259774757024567
    Line 327, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1652945394 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1652945394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.52784025141082360588195711131003364444563900776546501682835414460139790039736
    Line 146, in log /workspaces/repo/scratch/os_regression_2024_09_10/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 147806058 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 147806058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```