7e34e67ade| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | otbn_smoke | 1.896s | 0 | 1 | 0.00 | |
| V1 | single_binary | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V1 | csr_hw_reset | otbn_csr_hw_reset | 1.617m | 52.611us | 5 | 5 | 100.00 |
| V1 | csr_rw | otbn_csr_rw | 1.450m | 13.420us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otbn_csr_bit_bash | 1.433m | 628.007us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otbn_csr_aliasing | 1.317m | 52.121us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otbn_csr_mem_rw_with_rand_reset | 1.867m | 25.502us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otbn_csr_rw | 1.450m | 13.420us | 20 | 20 | 100.00 |
| otbn_csr_aliasing | 1.317m | 52.121us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otbn_mem_walk | 1.800m | 702.324us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otbn_mem_partial_access | 1.600m | 473.272us | 5 | 5 | 100.00 |
| V1 | TOTAL | 164 | 166 | 98.80 | |||
| V2 | reset_recovery | otbn_reset | 46.000s | 271.098us | 10 | 10 | 100.00 |
| V2 | multi_error | otbn_multi_err | 1.067m | 337.068us | 1 | 1 | 100.00 |
| V2 | back_to_back | otbn_multi | 2.983m | 2.516ms | 10 | 10 | 100.00 |
| V2 | stress_all | otbn_stress_all | 1.367m | 838.518us | 10 | 10 | 100.00 |
| V2 | lc_escalation | otbn_escalate | 1.167m | 26.051us | 54 | 60 | 90.00 |
| V2 | zero_state_err_urnd | otbn_zero_state_err_urnd | 12.000s | 25.629us | 5 | 5 | 100.00 |
| V2 | sw_errs_fatal_chk | otbn_sw_errs_fatal_chk | 18.000s | 58.313us | 10 | 10 | 100.00 |
| V2 | alert_test | otbn_alert_test | 1.317m | 23.066us | 50 | 50 | 100.00 |
| V2 | intr_test | otbn_intr_test | 1.467m | 24.852us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | otbn_tl_errors | 1.583m | 198.283us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otbn_tl_errors | 1.583m | 198.283us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otbn_csr_hw_reset | 1.617m | 52.611us | 5 | 5 | 100.00 |
| otbn_csr_rw | 1.450m | 13.420us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 1.317m | 52.121us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 1.183m | 23.378us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otbn_csr_hw_reset | 1.617m | 52.611us | 5 | 5 | 100.00 |
| otbn_csr_rw | 1.450m | 13.420us | 20 | 20 | 100.00 | ||
| otbn_csr_aliasing | 1.317m | 52.121us | 5 | 5 | 100.00 | ||
| otbn_same_csr_outstanding | 1.183m | 23.378us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 246 | 97.56 | |||
| V2S | mem_integrity | otbn_imem_err | 30.000s | 124.726us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 90.704us | 15 | 15 | 100.00 | ||
| V2S | internal_integrity | otbn_alu_bignum_mod_err | 12.000s | 435.600us | 5 | 5 | 100.00 |
| otbn_controller_ispr_rdata_err | 13.000s | 619.945us | 5 | 5 | 100.00 | ||
| otbn_mac_bignum_acc_err | 18.000s | 64.754us | 5 | 5 | 100.00 | ||
| otbn_urnd_err | 7.000s | 11.886us | 2 | 2 | 100.00 | ||
| V2S | illegal_bus_access | otbn_illegal_mem_acc | 15.000s | 36.764us | 5 | 5 | 100.00 |
| V2S | otbn_mem_gnt_acc_err | otbn_mem_gnt_acc_err | 9.000s | 108.870us | 2 | 2 | 100.00 |
| V2S | otbn_non_sec_partial_wipe | otbn_partial_wipe | 11.000s | 100.266us | 9 | 10 | 90.00 |
| V2S | tl_intg_err | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| otbn_tl_intg_err | 1.717m | 119.646us | 20 | 20 | 100.00 | ||
| V2S | passthru_mem_tl_intg_err | otbn_passthru_mem_tl_intg_err | 1.733m | 345.999us | 20 | 20 | 100.00 |
| V2S | prim_fsm_check | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | prim_count_check | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_mem_scramble | otbn_smoke | 1.896s | 0 | 1 | 0.00 | |
| V2S | sec_cm_data_mem_integrity | otbn_dmem_err | 18.000s | 90.704us | 15 | 15 | 100.00 |
| V2S | sec_cm_instruction_mem_integrity | otbn_imem_err | 30.000s | 124.726us | 10 | 10 | 100.00 |
| V2S | sec_cm_bus_integrity | otbn_tl_intg_err | 1.717m | 119.646us | 20 | 20 | 100.00 |
| V2S | sec_cm_controller_fsm_global_esc | otbn_escalate | 1.167m | 26.051us | 54 | 60 | 90.00 |
| V2S | sec_cm_controller_fsm_local_esc | otbn_imem_err | 30.000s | 124.726us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 90.704us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 25.629us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 15.000s | 36.764us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_controller_fsm_sparse | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_scramble_key_sideload | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_scramble_ctrl_fsm_local_esc | otbn_imem_err | 30.000s | 124.726us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 90.704us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 25.629us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 15.000s | 36.764us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_scramble_ctrl_fsm_sparse | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_global_esc | otbn_escalate | 1.167m | 26.051us | 54 | 60 | 90.00 |
| V2S | sec_cm_start_stop_ctrl_fsm_local_esc | otbn_imem_err | 30.000s | 124.726us | 10 | 10 | 100.00 |
| otbn_dmem_err | 18.000s | 90.704us | 15 | 15 | 100.00 | ||
| otbn_zero_state_err_urnd | 12.000s | 25.629us | 5 | 5 | 100.00 | ||
| otbn_illegal_mem_acc | 15.000s | 36.764us | 5 | 5 | 100.00 | ||
| otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 | ||
| V2S | sec_cm_start_stop_ctrl_fsm_sparse | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_data_reg_sw_sca | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_redun | otbn_ctrl_redun | 19.000s | 45.214us | 12 | 12 | 100.00 |
| V2S | sec_cm_pc_ctrl_flow_redun | otbn_pc_ctrl_flow_redun | 11.000s | 21.079us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_bus_consistency | otbn_rnd_sec_cm | 37.000s | 545.982us | 5 | 5 | 100.00 |
| V2S | sec_cm_rnd_rng_digest | otbn_rnd_sec_cm | 37.000s | 545.982us | 5 | 5 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_integrity | otbn_rf_base_intg_err | 14.000s | 84.619us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_base_data_reg_sw_glitch_detect | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_stack_wr_ptr_ctr_redun | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_integrity | otbn_rf_bignum_intg_err | 31.000s | 86.517us | 10 | 10 | 100.00 |
| V2S | sec_cm_rf_bignum_data_reg_sw_glitch_detect | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_ctr_redun | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | sec_cm_loop_stack_addr_integrity | otbn_stack_addr_integ_chk | 19.000s | 29.144us | 5 | 5 | 100.00 |
| V2S | sec_cm_call_stack_addr_integrity | otbn_stack_addr_integ_chk | 19.000s | 29.144us | 5 | 5 | 100.00 |
| V2S | sec_cm_start_stop_ctrl_state_consistency | otbn_sec_wipe_err | 20.000s | 108.387us | 7 | 7 | 100.00 |
| V2S | sec_cm_data_mem_sec_wipe | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_instruction_mem_sec_wipe | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_reg_sw_sec_wipe | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_write_mem_integrity | otbn_multi | 2.983m | 2.516ms | 10 | 10 | 100.00 |
| V2S | sec_cm_ctrl_flow_count | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_ctrl_flow_sca | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_data_mem_sw_noaccess | otbn_sw_no_acc | 17.000s | 99.224us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_sideload | otbn_single | 5.017m | 986.168us | 99 | 100 | 99.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | otbn_sec_cm | 7.083m | 1.923ms | 3 | 5 | 60.00 |
| V2S | TOTAL | 160 | 163 | 98.16 | |||
| V3 | stress_all_with_rand_reset | otbn_stress_all_with_rand_reset | 4.700m | 8.089ms | 5 | 10 | 50.00 |
| V3 | TOTAL | 5 | 10 | 50.00 | |||
| TOTAL | 569 | 585 | 97.26 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 7 | 77.78 |
| V2 | 11 | 11 | 10 | 90.91 |
| V2S | 20 | 20 | 18 | 90.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.96 | 99.60 | 95.36 | 99.69 | 93.41 | 92.98 | 100.00 | 98.85 | 99.16 |
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:
8.otbn_escalate.21928983289429507639277646017720959906550753067195512882948997939946251833325
Line 99, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/8.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 35154810 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 35154810 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 35154810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.otbn_escalate.98425605870472958324167598234074160501203919285562541883153830959478887771047
Line 102, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/18.otbn_escalate/latest/run.log
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 42438342 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 42438342 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 42438342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
2.otbn_stress_all_with_rand_reset.25004628378667562864880466068039810254753877683095481039221991597953096478096
Line 315, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1233253418 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1233253418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.otbn_stress_all_with_rand_reset.108736543098971082474978566928422059563422355342253373165011263709641561910298
Line 145, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 244607361 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 244607361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job returned non-zero exit code has 2 failures:
Test otbn_smoke has 1 failures.
0.otbn_smoke.111723537671889190648271344971749959871123444323366465528194216170399885299053
Log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest/run.log
make -f /workspaces/repo/hw/dv/tools/dvsim/sim.mk run build_seed=4190660412037082522497784440658734031572790705268868319466386425736861254975 post_run_cmds='' pre_run_cmds='pushd /workspaces/repo; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /workspaces/repo/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /workspaces/repo/hw/ip/otbn/dv/smoke /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest/otbn-binaries' proj_root=/workspaces/repo run_cmd=xrun run_dir=/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest run_opts='+otbn_elf_dir=/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /workspaces/repo/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=1021709677 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/coverage/default/0.otbn_smoke.1021709677 -covworkdir /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_smoke.1021709677 -covoverwrite' seed=111723537671889190648271344971749959871123444323366465528194216170399885299053 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_smoke_vseq
[make]: pre_run
mkdir -p /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest
cd /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest && pushd /workspaces/repo; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /workspaces/repo/hw/ip/otbn/dv/uvm/gen-binaries.py --src-dir /workspaces/repo/hw/ip/otbn/dv/smoke /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest/otbn-binaries
/workspaces/repo /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_smoke/latest
2024/09/18 19:15:07 Downloading https://releases.bazel.build/7.3.1/release/bazel-7.3.1-linux-x86_64...
Opening zip "/home/miguelosorio/.cache/bazelisk/downloads/bazelbuild/bazel-7.3.1-linux-x86_64/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/home/miguelosorio/.cache/bazelisk/downloads/bazelbuild/bazel-7.3.1-linux-x86_64/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
Test otbn_single has 1 failures.
0.otbn_single.107846561013588870912042790172278311058481470614006268085504549559740989475519
Log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest/run.log
make -f /workspaces/repo/hw/dv/tools/dvsim/sim.mk run build_seed=4190660412037082522497784440658734031572790705268868319466386425736861254975 post_run_cmds='' pre_run_cmds='pushd /workspaces/repo; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /workspaces/repo/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 107846561013588870912042790172278311058481470614006268085504549559740989475519 --size 2000 --count 1 /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest/otbn-binaries' proj_root=/workspaces/repo run_cmd=xrun run_dir=/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest run_opts='+otbn_elf_dir=/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /workspaces/repo/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=747145919 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_single_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/coverage/default/0.otbn_single.747145919 -covworkdir /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_single.747145919 -covoverwrite' seed=107846561013588870912042790172278311058481470614006268085504549559740989475519 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_single_vseq
[make]: pre_run
mkdir -p /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest
cd /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest && pushd /workspaces/repo; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /workspaces/repo/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 107846561013588870912042790172278311058481470614006268085504549559740989475519 --size 2000 --count 1 /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest/otbn-binaries
/workspaces/repo /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_single/latest
2024/09/18 19:15:07 Downloading https://releases.bazel.build/7.3.1/release/bazel-7.3.1-linux-x86_64...
Opening zip "/home/miguelosorio/.cache/bazelisk/downloads/bazelbuild/bazel-7.3.1-linux-x86_64/bin/bazel (deleted)": open(): No such file or directory
FATAL: Failed to open '/home/miguelosorio/.cache/bazelisk/downloads/bazelbuild/bazel-7.3.1-linux-x86_64/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:
0.otbn_sec_cm.59592848350020947957165688447536662717370593468845435080240372905955835529374
Line 94, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 56972777 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 56972777 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 56972777 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 56972777 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 56972777 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
4.otbn_sec_cm.38242503429969069690742550836118202642051454682274190683553792794777416632957
Line 154, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 220692720 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 220692720 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 220692720 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 220692720 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 220692720 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
7.otbn_stress_all_with_rand_reset.94134806942795557285021235981421182142026402725434601975332225362766226561428
Line 170, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/7.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 887679335 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 887679335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.otbn_stress_all_with_rand_reset.66711608923092128769983295116893611459605493083569744242289482835171488311120
Line 148, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/8.otbn_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 50427801 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
UVM_INFO @ 50427801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 2 failures:
9.otbn_escalate.115458593188570037197698940516879882892661367184796474646762385534953122433981
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/9.otbn_escalate/latest/run.log
UVM_ERROR @ 120847398 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (255 [0xff] vs 4 [0x4]) value for register otbn_reg_block.status
UVM_INFO @ 120847398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
53.otbn_escalate.30083568944815881891656121405978277895898125995325036105736695751757493412011
Line 99, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/53.otbn_escalate/latest/run.log
UVM_ERROR @ 5465422 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
UVM_INFO @ 5465422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:
8.otbn_partial_wipe.20970148639046022996045268300429926352526514784934706162951149297002324848065
Line 106, in log /workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/8.otbn_partial_wipe/latest/run.log
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 6414505 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
UVM_ERROR @ 6414505 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 6414505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---