OTBN Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	18.000s	45.550us	1	1	100.00
V1	single_binary	otbn_single	42.000s	133.552us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	15.000s	41.879us	5	5	100.00
V1	csr_rw	otbn_csr_rw	11.000s	27.944us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	14.000s	109.435us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	19.847us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	12.000s	35.396us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	11.000s	27.944us	20	20	100.00
		otbn_csr_aliasing	9.000s	19.847us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.050m	8.495ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	34.000s	4.285ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.183m	163.576us	10	10	100.00
V2	multi_error	otbn_multi_err	1.283m	173.368us	1	1	100.00
V2	back_to_back	otbn_multi	1.800m	273.741us	10	10	100.00
V2	stress_all	otbn_stress_all	2.817m	453.233us	10	10	100.00
V2	lc_escalation	otbn_escalate	2.183m	385.556us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	79.333us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	19.000s	39.974us	10	10	100.00
V2	alert_test	otbn_alert_test	20.000s	59.164us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	17.781us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	16.000s	96.049us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	16.000s	96.049us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	15.000s	41.879us	5	5	100.00
		otbn_csr_rw	11.000s	27.944us	20	20	100.00
		otbn_csr_aliasing	9.000s	19.847us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	36.731us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	15.000s	41.879us	5	5	100.00
		otbn_csr_rw	11.000s	27.944us	20	20	100.00
		otbn_csr_aliasing	9.000s	19.847us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	36.731us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	18.000s	28.650us	10	10	100.00
		otbn_dmem_err	22.000s	145.761us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	108.277us	5	5	100.00
		otbn_controller_ispr_rdata_err	17.000s	67.633us	5	5	100.00
		otbn_mac_bignum_acc_err	24.000s	52.288us	5	5	100.00
		otbn_urnd_err	10.000s	11.501us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	28.691us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	12.976us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	28.581us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
		otbn_tl_intg_err	49.000s	238.500us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	41.000s	380.253us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	18.000s	45.550us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	22.000s	145.761us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	18.000s	28.650us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	49.000s	238.500us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.183m	385.556us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	18.000s	28.650us	10	10	100.00
		otbn_dmem_err	22.000s	145.761us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	79.333us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	28.691us	5	5	100.00
		otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	18.000s	28.650us	10	10	100.00
		otbn_dmem_err	22.000s	145.761us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	79.333us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	28.691us	5	5	100.00
		otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.183m	385.556us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	18.000s	28.650us	10	10	100.00
		otbn_dmem_err	22.000s	145.761us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	79.333us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	28.691us	5	5	100.00
		otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	123.882us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	29.960us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.850m	1.366ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.850m	1.366ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	71.535us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	17.000s	61.904us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	62.883us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	62.883us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	23.000s	63.583us	2	7	28.57
V2S	sec_cm_data_mem_sec_wipe	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.800m	273.741us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	259.728us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	42.000s	133.552us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.650m	9.172ms	3	5	60.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.683m	1.745ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			572	585	97.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	18	90.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.99	99.61	95.53	99.70	93.52	93.15	100.00	98.85	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 0.otbn_stress_all_with_rand_reset.61005812394300182306104714158866108081062859777424301526679347842675100340150
    Line 382, in log /workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1745289818 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1745289818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otbn_stress_all_with_rand_reset.16777101464661058367970373532680527153599034195124351983172669581636247290882
    Line 398, in log /workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1058816777 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1058816777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 5 failures:

Test otbn_sec_wipe_err has 5 failures.

0.otbn_sec_wipe_err.58592125491425850063273510871667639463682661213621264824881287404949597167980
Line 103, in log /workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 63583341 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  63583341 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  63583341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_wipe_err.44003733833479582316126939660392776270875027889184617566499567968762434508140
Line 110, in log /workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 41585784 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  41585784 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  41585784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

1.otbn_sec_cm.78054640667239345159182558157453236236260224697789741829399042786044436541533
Line 115, in log /workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 502629762 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 502629762 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 502629762 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 502629762 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 502629762 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

4.otbn_sec_cm.101858553848380087117712531903120030634301322977196616428746830596196899716277
Line 116, in log /workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 222973022 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 222973022 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 222973022 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 222973022 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 222973022 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 11.otbn_escalate.4659145609857342911360370710946680108840532062394445898673031241195185152488
    Line 98, in log /workspaces/repo/scratch/os_regression_2024_10_08/otbn-sim-xcelium/11.otbn_escalate/latest/run.log
```
  UVM_ERROR @   2842400 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   2842400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```