OTBN Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: XCELIUM

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	19.000s	39.068us	1	1	100.00
V1	single_binary	otbn_single	1.817m	1.612ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	79.516us	5	5	100.00
V1	csr_rw	otbn_csr_rw	35.000s	102.280us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	208.587us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	22.557us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	46.000s	136.052us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	35.000s	102.280us	20	20	100.00
		otbn_csr_aliasing	8.000s	22.557us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.100m	16.933ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	30.000s	447.272us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.050m	183.178us	10	10	100.00
V2	multi_error	otbn_multi_err	2.117m	232.827us	1	1	100.00
V2	back_to_back	otbn_multi	4.067m	957.270us	10	10	100.00
V2	stress_all	otbn_stress_all	1.567m	201.242us	10	10	100.00
V2	lc_escalation	otbn_escalate	1.317m	813.340us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	46.503us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	36.000s	76.202us	10	10	100.00
V2	alert_test	otbn_alert_test	11.000s	19.905us	50	50	100.00
V2	intr_test	otbn_intr_test	39.000s	16.304us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	55.000s	82.362us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	55.000s	82.362us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	79.516us	5	5	100.00
		otbn_csr_rw	35.000s	102.280us	20	20	100.00
		otbn_csr_aliasing	8.000s	22.557us	5	5	100.00
		otbn_same_csr_outstanding	36.000s	394.092us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	79.516us	5	5	100.00
		otbn_csr_rw	35.000s	102.280us	20	20	100.00
		otbn_csr_aliasing	8.000s	22.557us	5	5	100.00
		otbn_same_csr_outstanding	36.000s	394.092us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	18.000s	28.565us	10	10	100.00
		otbn_dmem_err	24.000s	38.381us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	16.000s	83.384us	5	5	100.00
		otbn_controller_ispr_rdata_err	37.000s	75.281us	5	5	100.00
		otbn_mac_bignum_acc_err	32.000s	81.712us	5	5	100.00
		otbn_urnd_err	20.000s	39.277us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	15.000s	26.940us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	40.027us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	16.000s	44.834us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
		otbn_tl_intg_err	50.000s	318.688us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	52.000s	2.922ms	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	19.000s	39.068us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	24.000s	38.381us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	18.000s	28.565us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	50.000s	318.688us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	1.317m	813.340us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	18.000s	28.565us	10	10	100.00
		otbn_dmem_err	24.000s	38.381us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	46.503us	5	5	100.00
		otbn_illegal_mem_acc	15.000s	26.940us	5	5	100.00
		otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	18.000s	28.565us	10	10	100.00
		otbn_dmem_err	24.000s	38.381us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	46.503us	5	5	100.00
		otbn_illegal_mem_acc	15.000s	26.940us	5	5	100.00
		otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	1.317m	813.340us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	18.000s	28.565us	10	10	100.00
		otbn_dmem_err	24.000s	38.381us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	46.503us	5	5	100.00
		otbn_illegal_mem_acc	15.000s	26.940us	5	5	100.00
		otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	1.333m	474.312us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	46.254us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	46.000s	409.072us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	46.000s	409.072us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	25.000s	50.725us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	36.000s	329.082us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	110.043us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	110.043us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	16.000s	154.614us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.067m	957.270us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	23.000s	182.745us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.817m	1.612ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	10.500m	2.089ms	2	5	40.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	6.450m	3.610ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			568	585	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	16	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.92	99.59	95.18	99.69	93.55	92.43	100.00	98.39	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test otbn_stress_all_with_rand_reset has 4 failures.
  - 3.otbn_stress_all_with_rand_reset.56038024913635076994032370063792780047636508413706178248272745331054172570065
    Line 302, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1939623588 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1939623588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otbn_stress_all_with_rand_reset.98901257238035027660803370948617423260103497614286644660543445850464176648585
    Line 163, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 579435218 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 579435218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.40137302000985833143718253378924955654616575136664611422462332493785263340207
Line 134, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 72604120 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 72604120 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 72604120 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 72604120 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 72604120 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.34497930798535135854502358351760099894431524953443726460810006982855402954019
Line 123, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 97579182 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 97579182 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 97579182 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 97579182 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 97579182 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 1 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 2 failures.

2.otbn_sec_wipe_err.41183366906348433114764317561277762809353832301036173728364223082543422223215
Line 109, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 228802308 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 228802308 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 228802308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otbn_sec_wipe_err.54165274398552976791817612182787895952546405834144042575607018903301152147424
Line 106, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 154613788 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 154613788 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 154613788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

22.otbn_escalate.114735727438289546537977471956565754335576962442867667962501142303990150821783
Line 105, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/22.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11630103 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11630103 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11630103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.40354094674187252658676271082918188888321572844661720103740256577551582480857
    Line 182, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 106932960 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 106932960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.otbn_stress_all_with_rand_reset.71852123526719711768853912764827362427947973819982173518838062645633183137612
    Line 369, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 573872978 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 573872978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 2 failures:

Test otbn_escalate has 2 failures.

38.otbn_escalate.77168768889568281314085847540153004580722986994956387679124961461413832272684
Line 99, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/38.otbn_escalate/latest/run.log

  UVM_ERROR @   2923174 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   2923174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

58.otbn_escalate.103294360058015688361785720820466735995693058983626553619383403547487153904101
Line 98, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/58.otbn_escalate/latest/run.log

  UVM_ERROR @   1457501 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   1457501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.28038535018266537875006534525799724089566076099602614433875200793908703145340
    Line 290, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4597039067 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 4597039067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,287): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 3.otbn_partial_wipe.6282187746021194487103445594266138905245378706107277451236324476971232869095
    Line 110, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,287): (time 22695993 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @  22695993 ps: (tb.sv:287) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @  22695993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,137): Assertion NoModelErrs has failed has 1 failures:
- Test otbn_ctrl_redun has 1 failures.
  - 8.otbn_ctrl_redun.79385673013752927690568502375124699829651026001086094181360026626517387088020
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/8.otbn_ctrl_redun/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_23/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 474311790 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @ 474311790 ps: (otbn_model_if.sv:137) [ASSERT FAILED] NoModelErrs
  UVM_INFO @ 474311790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```