OTBN Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: XCELIUM

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	18.000s	403.461us	1	1	100.00
V1	single_binary	otbn_single	2.083m	572.784us	99	100	99.00
V1	csr_hw_reset	otbn_csr_hw_reset	44.000s	41.668us	5	5	100.00
V1	csr_rw	otbn_csr_rw	56.000s	37.820us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	44.000s	82.495us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	20.000s	19.003us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	55.000s	137.547us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	56.000s	37.820us	20	20	100.00
		otbn_csr_aliasing	20.000s	19.003us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.050m	29.803ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	30.000s	685.281us	5	5	100.00
V1		TOTAL			165	166	99.40
V2	reset_recovery	otbn_reset	45.000s	329.736us	10	10	100.00
V2	multi_error	otbn_multi_err	1.150m	1.413ms	1	1	100.00
V2	back_to_back	otbn_multi	2.017m	287.641us	10	10	100.00
V2	stress_all	otbn_stress_all	2.250m	584.009us	10	10	100.00
V2	lc_escalation	otbn_escalate	24.000s	42.800us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	16.000s	162.884us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	26.000s	58.839us	10	10	100.00
V2	alert_test	otbn_alert_test	13.000s	35.500us	50	50	100.00
V2	intr_test	otbn_intr_test	55.000s	64.963us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	1.350m	127.813us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	1.350m	127.813us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	44.000s	41.668us	5	5	100.00
		otbn_csr_rw	56.000s	37.820us	20	20	100.00
		otbn_csr_aliasing	20.000s	19.003us	5	5	100.00
		otbn_same_csr_outstanding	52.000s	63.962us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	44.000s	41.668us	5	5	100.00
		otbn_csr_rw	56.000s	37.820us	20	20	100.00
		otbn_csr_aliasing	20.000s	19.003us	5	5	100.00
		otbn_same_csr_outstanding	52.000s	63.962us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	15.000s	76.750us	10	10	100.00
		otbn_dmem_err	1.650m	310.102us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	13.000s	68.430us	5	5	100.00
		otbn_controller_ispr_rdata_err	18.000s	120.180us	5	5	100.00
		otbn_mac_bignum_acc_err	2.467m	449.843us	5	5	100.00
		otbn_urnd_err	12.000s	18.051us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	18.000s	34.867us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	31.335us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	14.000s	30.785us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
		otbn_tl_intg_err	1.683m	332.379us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	2.000m	458.425us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	18.000s	403.461us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	1.650m	310.102us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	15.000s	76.750us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.683m	332.379us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	24.000s	42.800us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	15.000s	76.750us	10	10	100.00
		otbn_dmem_err	1.650m	310.102us	15	15	100.00
		otbn_zero_state_err_urnd	16.000s	162.884us	5	5	100.00
		otbn_illegal_mem_acc	18.000s	34.867us	5	5	100.00
		otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	15.000s	76.750us	10	10	100.00
		otbn_dmem_err	1.650m	310.102us	15	15	100.00
		otbn_zero_state_err_urnd	16.000s	162.884us	5	5	100.00
		otbn_illegal_mem_acc	18.000s	34.867us	5	5	100.00
		otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	24.000s	42.800us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	15.000s	76.750us	10	10	100.00
		otbn_dmem_err	1.650m	310.102us	15	15	100.00
		otbn_zero_state_err_urnd	16.000s	162.884us	5	5	100.00
		otbn_illegal_mem_acc	18.000s	34.867us	5	5	100.00
		otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	60.741us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	20.000s	51.747us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	35.000s	201.943us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	35.000s	201.943us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	17.000s	22.576us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	16.000s	65.062us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	33.000s	90.262us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	33.000s	90.262us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	22.000s	65.658us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.017m	287.641us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	60.442us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.083m	572.784us	99	100	99.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	9.367m	27.047ms	3	5	60.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	4.267m	3.169ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.94	99.60	95.36	99.69	93.47	92.68	100.00	98.51	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 2.otbn_stress_all_with_rand_reset.81165015809835791174773249768600293546839047787537480305025696265344865263477
    Line 146, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 393767880 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 393767880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.107504030136552417164331587502382603669532726155667901667479416977253293645167
    Line 170, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 310637219 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 310637219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 3 failures.

2.otbn_sec_wipe_err.84636146531948599864151351839720696980827710860261038040877832635624878146299
Line 105, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15126578 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15126578 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15126578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.64190304963192208057373262029024724395090626111926678199351412459724041637400
Line 107, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 18805534 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  18805534 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  18805534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_escalate has 1 failures.

54.otbn_escalate.14560234526695602795583342069223947111845318723024300625510275765316541208413
Line 110, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/54.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 102081121 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 102081121 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 102081121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

0.otbn_sec_cm.27931302045816534038969913484807659191171944029058148975982582544053678292133
Line 151, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 87544332 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 87544332 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 87544332 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 87544332 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 87544332 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

3.otbn_sec_cm.61605316122514129747974452218423077956177113926789704117806945710084805739216
Line 128, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 101849001 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 101849001 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 101849001 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 101849001 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 101849001 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,289): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 5.otbn_partial_wipe.74668153815290416966958271335934418547394649709122783284636095576875628796209
    Line 102, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/5.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,289): (time 6610059 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   6610059 ps: (tb.sv:289) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   6610059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 9.otbn_stress_all_with_rand_reset.49697589372164985462106840114403078797655986953415793301111152031480661105638
    Line 147, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  57066701 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  57066701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 40.otbn_escalate.102053627493685656003427213441862436285916394341493966887311581430863812204289
    Line 96, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/40.otbn_escalate/latest/run.log
```
  UVM_ERROR @   1472950 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   1472950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_single has 1 failures.
  - 49.otbn_single.50037386311725870198595373787389619030942671406393213446744728872985282363088
    Line 96, in log /workspaces/repo/scratch/os_regression_2024_10_11/otbn-sim-xcelium/49.otbn_single/latest/run.log
```
  UVM_FATAL @  32649902 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  32649902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```