OTBN Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: XCELIUM

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	16.000s	128.945us	1	1	100.00
V1	single_binary	otbn_single	1.867m	416.364us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	29.000s	51.250us	5	5	100.00
V1	csr_rw	otbn_csr_rw	1.067m	160.671us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	39.000s	590.245us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	42.000s	20.612us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	48.000s	96.670us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	1.067m	160.671us	20	20	100.00
		otbn_csr_aliasing	42.000s	20.612us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.167m	3.728ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	1.067m	444.152us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.033m	230.350us	10	10	100.00
V2	multi_error	otbn_multi_err	1.033m	503.362us	1	1	100.00
V2	back_to_back	otbn_multi	2.233m	393.786us	10	10	100.00
V2	stress_all	otbn_stress_all	3.333m	650.246us	10	10	100.00
V2	lc_escalation	otbn_escalate	32.000s	517.893us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	55.245us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	57.000s	124.454us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	22.625us	50	50	100.00
V2	intr_test	otbn_intr_test	44.000s	22.014us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	1.083m	431.298us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	1.083m	431.298us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	29.000s	51.250us	5	5	100.00
		otbn_csr_rw	1.067m	160.671us	20	20	100.00
		otbn_csr_aliasing	42.000s	20.612us	5	5	100.00
		otbn_same_csr_outstanding	41.000s	115.594us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	29.000s	51.250us	5	5	100.00
		otbn_csr_rw	1.067m	160.671us	20	20	100.00
		otbn_csr_aliasing	42.000s	20.612us	5	5	100.00
		otbn_same_csr_outstanding	41.000s	115.594us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	22.000s	55.975us	10	10	100.00
		otbn_dmem_err	16.000s	63.892us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	842.320us	5	5	100.00
		otbn_controller_ispr_rdata_err	20.000s	39.743us	5	5	100.00
		otbn_mac_bignum_acc_err	24.000s	39.602us	5	5	100.00
		otbn_urnd_err	21.000s	59.289us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	18.337us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	12.000s	23.085us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	14.000s	34.945us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
		otbn_tl_intg_err	1.133m	216.175us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.383m	705.290us	20	20	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	prim_count_check	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_mem_scramble	otbn_smoke	16.000s	128.945us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	16.000s	63.892us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	22.000s	55.975us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.133m	216.175us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	32.000s	517.893us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	22.000s	55.975us	10	10	100.00
		otbn_dmem_err	16.000s	63.892us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	55.245us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	18.337us	5	5	100.00
		otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	22.000s	55.975us	10	10	100.00
		otbn_dmem_err	16.000s	63.892us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	55.245us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	18.337us	5	5	100.00
		otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	32.000s	517.893us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	22.000s	55.975us	10	10	100.00
		otbn_dmem_err	16.000s	63.892us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	55.245us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	18.337us	5	5	100.00
		otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	18.000s	36.247us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	15.000s	57.385us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.067m	827.564us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.067m	827.564us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	22.000s	47.432us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	22.000s	87.507us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	24.000s	60.522us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	24.000s	60.522us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	60.525us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.233m	393.786us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	18.000s	112.724us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.867m	416.364us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.350m	5.472ms	1	5	20.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	11.633m	2.097ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			570	585	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	20	20	17	85.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.98	99.61	95.49	99.71	93.55	93.00	100.00	98.62	99.16

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:
- Test otbn_stress_all_with_rand_reset has 5 failures.
  - 2.otbn_stress_all_with_rand_reset.34771829070857995210912550552603203599813626854024251812698722072241619924641
    Line 194, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1102149294 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1102149294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otbn_stress_all_with_rand_reset.52303468392940874861759700055726205180337987333884663670999999499941794989526
    Line 355, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2586920637 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2586920637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 2 failures.

0.otbn_sec_wipe_err.39394374774418659193240909607207153689033743992858993811320010495267664958022
Line 126, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 13603223 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  13603223 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  13603223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_wipe_err.9536930249877892563069134326470180293035890055940245380828148653947493341251
Line 107, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/4.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 60524924 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  60524924 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  60524924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_ctrl_redun has 1 failures.

11.otbn_ctrl_redun.46923976932877304858086436207475720582365456561517532651516349747322734700087
Line 105, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/11.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21713932 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  21713932 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  21713932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

13.otbn_escalate.31608380060079299848912300911289087259439837037219183703102190802578931863642
Line 107, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/13.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 122495738 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 122495738 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 122495738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1373): Assertion ErrBitsKnown_A has failed has 4 failures:

Test otbn_sec_cm has 4 failures.

0.otbn_sec_cm.5709498983223892240278249217101581328778537905211780297592738226289847697500
Line 98, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 28180871 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 28180871 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 28180871 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 28180871 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 28180871 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

1.otbn_sec_cm.45293233012133627994331783906292424340009401382703935075328409267517543327952
Line 157, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1373): (time 374356828 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 374356828 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 374356828 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 374356828 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 374356828 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed

... and 2 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 0.otbn_stress_all_with_rand_reset.113629849745201768301225949288858787822884711617742061822789530365349640235381
    Line 149, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  10788194 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  10788194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otbn_stress_all_with_rand_reset.30272948054674568372987693667804999724875883023006386063790617207618889622399
    Line 150, in log /workspaces/repo/scratch/os_regression_2024_10_02/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  80723420 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  80723420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```