OTP_CTRL Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.870s	237.976us	1	1	100.00
V1	smoke	otp_ctrl_smoke	21.470s	2.579ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.470s	1.364ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.300s	592.553us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.680s	1.726ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.140s	145.124us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.050s	1.431ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.300s	592.553us	20	20	100.00
		otp_ctrl_csr_aliasing	4.140s	145.124us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.360s	133.315us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.350s	487.303us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	16.910s	604.864us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.210s	2.735ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	23.900s	2.275ms	10	10	100.00
		otp_ctrl_check_fail	25.940s	9.606ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.630s	5.082ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	53.640s	25.973ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	33.090s	12.791ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	25.260s	9.931ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	16.630s	6.353ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	47.370s	13.236ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	36.700s	15.807ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	3.059m	31.149ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.890s	534.907us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.810s	829.155us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.430s	2.427ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.430s	2.427ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.470s	1.364ms	5	5	100.00
		otp_ctrl_csr_rw	2.300s	592.553us	20	20	100.00
		otp_ctrl_csr_aliasing	4.140s	145.124us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.120s	136.854us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.470s	1.364ms	5	5	100.00
		otp_ctrl_csr_rw	2.300s	592.553us	20	20	100.00
		otp_ctrl_csr_aliasing	4.140s	145.124us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.120s	136.854us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
		otp_ctrl_tl_intg_err	22.330s	2.101ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	22.330s	2.101ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	21.470s	2.579ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	21.470s	2.579ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
		otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
		otp_ctrl_macro_errs	47.370s	13.236ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
		otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
		otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
		otp_ctrl_macro_errs	47.370s	13.236ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	12.220s	3.937ms	200	200	100.00
		otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.210s	2.735ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	25.940s	9.606ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	53.640s	25.973ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	53.640s	25.973ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	53.640s	25.973ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	53.640s	25.973ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	53.640s	25.973ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	21.470s	2.579ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	53.640s	25.973ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	21.470s	2.579ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.040m	131.951ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.630s	5.082ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	21.470s	2.579ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	21.470s	2.579ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	47.370s	13.236ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.390s	3.077ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.971h	3.627s	90	100	90.00
V3		TOTAL			91	101	90.10
		TOTAL			1333	1343	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.48	92.67	91.67	92.31	92.39	93.51	96.53	95.27

Failure Buckets

• Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 3.otp_ctrl_stress_all_with_rand_reset.947367000
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:ecdec7ac-03a6-4f20-9cb0-e490d2e4981f
      

    • 5.otp_ctrl_stress_all_with_rand_reset.3811542720
      Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:7dc5216c-06e7-49cf-80b8-82517eb4777f
      

    • ... and 4 more failures.

• UVM_ERROR (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == * (* [*] vs * [*]) has 4 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 33.otp_ctrl_stress_all_with_rand_reset.1366054289
      Line 768, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1669471278951 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1669471278951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.otp_ctrl_stress_all_with_rand_reset.3615364405
      Line 306, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11526305031 ps: (tl_reg_adapter.sv:94) [m_tl_reg_adapter_otp_ctrl_prim_reg_block] Check failed bus_rsp.d_error == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 11526305031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

Past Results

• Latest
• 2023.05.21_20.15.38
• 2023.05.20_19.32.03
• 2023.05.19_16.13.05
• 2023.05.18_19.15.40
• 2023.05.17_17.59.32
• 2023.05.16_19.23.36
• 2023.05.15_18.41.17