OTP_CTRL Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.950s	178.119us	1	1	100.00
V1	smoke	otp_ctrl_smoke	45.160s	6.013ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.450s	215.243us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.730s	615.268us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.850s	1.363ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.470s	1.931ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.610s	1.537ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.730s	615.268us	20	20	100.00
		otp_ctrl_csr_aliasing	5.470s	1.931ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.900s	537.198us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.880s	520.939us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	16.230s	325.999us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.700s	2.617ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	27.440s	19.401ms	10	10	100.00
		otp_ctrl_check_fail	1.086m	7.619ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	9.330s	1.129ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	44.720s	4.595ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	34.010s	1.808ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	25.210s	10.424ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	17.100s	8.449ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.258m	7.392ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	31.260s	13.588ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	4.391m	47.889ms	48	50	96.00
V2	intr_test	otp_ctrl_intr_test	2.250s	568.812us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.120s	271.361us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.570s	590.365us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.570s	590.365us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.450s	215.243us	5	5	100.00
		otp_ctrl_csr_rw	1.730s	615.268us	20	20	100.00
		otp_ctrl_csr_aliasing	5.470s	1.931ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.420s	446.714us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.450s	215.243us	5	5	100.00
		otp_ctrl_csr_rw	1.730s	615.268us	20	20	100.00
		otp_ctrl_csr_aliasing	5.470s	1.931ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.420s	446.714us	20	20	100.00
V2		TOTAL			1099	1101	99.82
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
		otp_ctrl_tl_intg_err	29.550s	19.128ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	29.550s	19.128ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	45.160s	6.013ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	45.160s	6.013ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
		otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
		otp_ctrl_macro_errs	1.258m	7.392ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
		otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
		otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
		otp_ctrl_macro_errs	1.258m	7.392ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	13.930s	4.269ms	200	200	100.00
		otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.700s	2.617ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.086m	7.619ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	44.720s	4.595ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	44.720s	4.595ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	44.720s	4.595ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	44.720s	4.595ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	44.720s	4.595ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	45.160s	6.013ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	44.720s	4.595ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	45.160s	6.013ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	2.635m	17.780ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	9.330s	1.129ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	45.160s	6.013ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	45.160s	6.013ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.258m	7.392ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.380s	7.481ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.939h	7.240s	94	100	94.00
V3		TOTAL			95	101	94.06
		TOTAL			1335	1343	99.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.44	92.61	91.44	92.39	92.39	93.55	96.53	95.19

Failure Buckets

Job otp_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 63.otp_ctrl_stress_all_with_rand_reset.8026107705503673395645206025008329969859276510513263573374945524428356516365
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:c2fe9a75-40a1-42b5-ab09-702be1a3bfc3
```
  - 85.otp_ctrl_stress_all_with_rand_reset.42276593228560824401299286523534237161620262771481487357728298457397051793046
    Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:49686752-4475-4e10-9ac7-aaa2cc0cb78f
```
  - ... and 1 more failures.
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.94512028636654247192930977265522725882878208991732458768450422144164445005637
    Line 592, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 417960977645 ps: (otp_ctrl_if.sv:262) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 417960977645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@767507) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

18.otp_ctrl_stress_all.1204806711914920796293071429564084884495927506743815498173320797030796312203
Line 293, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 8490268751 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@767507) { a_addr: 'h42924468  a_data: 'h574b2a1c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h52  a_opcode: 'h0  a_user: 'h27160  d_param: 'h0  d_source: 'h52  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 8490268751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@50305982) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 27.otp_ctrl_stress_all_with_rand_reset.53750596723991147998071793178280208227708301933029652455223426085452654378937
    Line 1711, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 364655042207 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@50305982) { a_addr: 'hd2e6f72c  a_data: 'he53b446d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8f  a_opcode: 'h1  a_user: 'h275e3  d_param: 'h0  d_source: 'h8f  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 364655042207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@589103) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

43.otp_ctrl_stress_all.56372832343519836374537281181321983217339149410734669326157302458418330924632
Line 313, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 85677847808 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@589103) { a_addr: 'h52366ee8  a_data: 'he2afef2f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5a  a_opcode: 'h0  a_user: 'h25516  d_param: 'h0  d_source: 'h5a  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 85677847808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1345) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2840049) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 75.otp_ctrl_stress_all_with_rand_reset.62719930012840806740057419304944877676616310446844020508421613083779410800013
    Line 382, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16794987771 ps: (otp_ctrl_scoreboard.sv:1345) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@2840049) { a_addr: 'hcd1d9d4  a_data: 'hdd2fa247  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h72  a_opcode: 'h0  a_user: 'h2735b  d_param: 'h0  d_source: 'h72  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 16794987771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```