OTP_CTRL Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	62.270us	1	1	100.00
V1	smoke	otp_ctrl_smoke	15.540s	7.224ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.000s	1.424ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.830s	85.666us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.680s	545.915us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.850s	533.000us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.890s	1.638ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.830s	85.666us	20	20	100.00
		otp_ctrl_csr_aliasing	6.850s	533.000us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.490s	119.498us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.980s	524.149us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.720s	1.246ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.510s	3.159ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.004m	27.079ms	10	10	100.00
		otp_ctrl_check_fail	1.023m	20.950ms	44	50	88.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.670s	4.745ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.186m	7.940ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	55.510s	7.591ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.460s	1.796ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.610s	17.991ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.233m	31.420ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.043m	28.793ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	8.815m	41.657ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.180s	598.418us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.620s	969.358us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.950s	3.072ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.950s	3.072ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.000s	1.424ms	5	5	100.00
		otp_ctrl_csr_rw	1.830s	85.666us	20	20	100.00
		otp_ctrl_csr_aliasing	6.850s	533.000us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.280s	507.086us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.000s	1.424ms	5	5	100.00
		otp_ctrl_csr_rw	1.830s	85.666us	20	20	100.00
		otp_ctrl_csr_aliasing	6.850s	533.000us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.280s	507.086us	20	20	100.00
V2		TOTAL			1094	1101	99.36
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
		otp_ctrl_tl_intg_err	28.970s	18.893ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	28.970s	18.893ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	15.540s	7.224ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	15.540s	7.224ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
		otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
		otp_ctrl_macro_errs	1.233m	31.420ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
		otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
		otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
		otp_ctrl_macro_errs	1.233m	31.420ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	31.680s	11.082ms	200	200	100.00
		otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.510s	3.159ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.023m	20.950ms	44	50	88.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.186m	7.940ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.186m	7.940ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.186m	7.940ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.186m	7.940ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.186m	7.940ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	15.540s	7.224ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.186m	7.940ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	15.540s	7.224ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.939m	154.599ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.670s	4.745ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	15.540s	7.224ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	15.540s	7.224ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.233m	31.420ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.890s	3.046ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	49.672m	873.044ms	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1314	1343	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.86	96.76	95.55	90.93	97.42	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 5.otp_ctrl_stress_all_with_rand_reset.39340162910064777947502552694173872279976210388440325442059860502231473333841
    Line 53898, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79997199365 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 79997199365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.otp_ctrl_stress_all_with_rand_reset.64119071737553298467166786991438535231999667060424661345059828832025406497053
    Line 71843, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13579473800 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 13579473800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.71197758335448753442915952240919109512540060367257962584388891640492509977861
    Line 779, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 323459170 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3670693114 [0xdaca54fa] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 323459170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.otp_ctrl_stress_all_with_rand_reset.57998474699491279442756459088862394034261832822344330651974576238502731550469
    Line 94334, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 261893458970 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4219181032 [0xfb7b97e8] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 261893458970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 6 failures:
- Test otp_ctrl_check_fail has 6 failures.
  - 9.otp_ctrl_check_fail.28351201394186554228958949982487686466600066650369066964333317333022473990892
    Line 7469, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 231781599 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 231781599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_check_fail.33768133354447964192010921530717485105271333444465099814420383232513634292433
    Line 13036, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 1634775163 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 1634775163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 40.otp_ctrl_stress_all_with_rand_reset.105975950605644855646389204721635729217745243586215320590463022981829671766004
    Line 31400, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 379278500359 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 379278500359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.otp_ctrl_stress_all_with_rand_reset.47015908564774098067775523872561868219661694446836328105715380860336303616823
    Line 41366, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43932220935 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 43932220935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 26.otp_ctrl_stress_all_with_rand_reset.109918526430119102818433524025634440652872322629061624732501788347339357619266
    Line 14571, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 130516304774 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 130516304774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@159461) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

43.otp_ctrl_test_access.1599661331621082921482863151279836237025060776178083856133624582913467887189
Line 9438, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 465521097 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@159461) { a_addr: 'h65404c0c  a_data: 'h2ce2d8cc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd7  a_opcode: 'h0  a_user: 'h27205  d_param: 'h0  d_source: 'hd7  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 465521097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@12349778) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 56.otp_ctrl_stress_all_with_rand_reset.106666815992807444893623996769717789713572883887904274958396008519528438020439
    Line 66694, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 537359326780 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@12349778) { a_addr: 'h667a97d0  a_data: 'haf55ea24  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc2  a_opcode: 'h1  a_user: 'h2423f  d_param: 'h0  d_source: 'hc2  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 537359326780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 76.otp_ctrl_stress_all_with_rand_reset.83231379606185718155764138572904628943798338497000546034700141486721102259163
    Line 34939, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 499540474793 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2793837877 [0xa6869535]) dai addr 794 rdata0 readout mismatch
  UVM_INFO @ 499540474793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```