OTP_CTRL Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.890s	54.231us	1	1	100.00
V1	smoke	otp_ctrl_smoke	23.050s	7.280ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.560s	192.392us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.420s	616.723us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	20.460s	7.671ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.760s	757.739us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.550s	1.717ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.420s	616.723us	20	20	100.00
		otp_ctrl_csr_aliasing	6.760s	757.739us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.990s	546.427us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.680s	535.316us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.450s	825.136us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.600s	2.310ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	57.880s	18.621ms	10	10	100.00
		otp_ctrl_check_fail	1.059m	6.325ms	49	50	98.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.900s	4.608ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.058m	8.108ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	45.510s	3.446ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	40.020s	13.237ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.115m	16.845ms	48	50	96.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.420m	13.414ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	59.010s	23.591ms	49	50	98.00
V2	stress_all	otp_ctrl_stress_all	11.815m	167.253ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.210s	606.793us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.500s	1.131ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.330s	3.439ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.330s	3.439ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.560s	192.392us	5	5	100.00
		otp_ctrl_csr_rw	2.420s	616.723us	20	20	100.00
		otp_ctrl_csr_aliasing	6.760s	757.739us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.450s	1.811ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.560s	192.392us	5	5	100.00
		otp_ctrl_csr_rw	2.420s	616.723us	20	20	100.00
		otp_ctrl_csr_aliasing	6.760s	757.739us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.450s	1.811ms	20	20	100.00
V2		TOTAL			1096	1101	99.55
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
		otp_ctrl_tl_intg_err	49.840s	19.994ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	49.840s	19.994ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	23.050s	7.280ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	23.050s	7.280ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
		otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
		otp_ctrl_macro_errs	2.420m	13.414ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
		otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
		otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
		otp_ctrl_macro_errs	2.420m	13.414ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	49.200s	12.840ms	200	200	100.00
		otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.600s	2.310ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.059m	6.325ms	49	50	98.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.058m	8.108ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.058m	8.108ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.058m	8.108ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.058m	8.108ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.058m	8.108ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	23.050s	7.280ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.058m	8.108ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	23.050s	7.280ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.653m	41.336ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.900s	4.608ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	23.050s	7.280ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	23.050s	7.280ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.420m	13.414ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	19.000s	3.405ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.070h	1.759s	86	100	86.00
V3		TOTAL			87	101	86.14
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	13	76.47
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.26	94.00	97.19	95.98	92.36	97.70	96.33	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.51616003971643944916938672546681597151218368596223608822852254106638202093874
    Line 4080, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 364258186 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 364258186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.otp_ctrl_stress_all_with_rand_reset.58379853426089134711114453118912845134200036196081749283994984656157056244767
    Line 18465, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23882484244 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 23882484244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.73206651195542018090286030715156123641830901164771580807093886777631361730108
    Line 52153, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46037465129 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (997237127 [0x3b70a187] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 46037465129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.otp_ctrl_stress_all_with_rand_reset.92887054314139135357336148337586363410542314994715897987216073497435387921767
    Line 10731, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 40211720881 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (259037495 [0xf709937] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 40211720881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr ceeb5e*, csr_addr * has 1 failures:
- Test otp_ctrl_dai_errs has 1 failures.
  - 8.otp_ctrl_dai_errs.103815065488738335720088597619810131963732193013742955974403688080274307598641
    Line 3893, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest/run.log
```
  UVM_ERROR @ 738167353 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (3489658879 [0xcffff7ff] vs 783771239 [0x2eb76667]) mem read mismatch at TLUL addr ceeb5e70, csr_addr 670
  UVM_INFO @ 738167353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@992974) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

22.otp_ctrl_stress_all.92873321853144577930013284467392703889660020325518746693608606765156732765419
Line 60546, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 36011387973 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@992974) { a_addr: 'h8ac64278  a_data: 'hf8633194  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h0  a_user: 'h24b94  d_param: 'h0  d_source: 'h22  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 36011387973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@28507) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

27.otp_ctrl_test_access.40790551876827145007829789170978277357860560466723505607166872851787641343575
Line 1588, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 127756659 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@28507) { a_addr: 'h56b41130  a_data: 'h770b2c5f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h49  a_opcode: 'h0  a_user: 'h24b2f  d_param: 'h0  d_source: 'h49  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 127756659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:608) [scoreboard] Check failed item.d_data == otp_a[otp_addr] (* [*] vs * [*]) mem read mismatch at TLUL addr fca00e*, csr_addr * has 1 failures:
- Test otp_ctrl_dai_errs has 1 failures.
  - 37.otp_ctrl_dai_errs.90359992615530368364623382964965933426468089597618002839033333194808190254624
    Line 4436, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest/run.log
```
  UVM_ERROR @ 118431834 ps: (otp_ctrl_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed item.d_data == otp_a[otp_addr] (1572194519 [0x5db5c8d7] vs 353749218 [0x1515c8e2]) mem read mismatch at TLUL addr fca00e70, csr_addr 670
  UVM_INFO @ 118431834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:-* has 1 failures:
- Test otp_ctrl_check_fail has 1 failures.
  - 41.otp_ctrl_check_fail.59125560335069573538876282721938348526328119200443272031767818508610008045247
    Line 3938, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest/run.log
```
  UVM_ERROR @ 435672090 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:-1
  UVM_INFO @ 435672090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

97.otp_ctrl_stress_all_with_rand_reset.62423178601356115379187539185780167300644770154305262699760165440003240636107
Line 3995, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 14710219824 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 14710428154 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 14710553152 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 14711407305 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 14711532303 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1