OTP_CTRL Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.710s	106.172us	1	1	100.00
V1	smoke	otp_ctrl_smoke	47.360s	7.587ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.830s	1.046ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.570s	574.623us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	13.570s	2.023ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.660s	410.575us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.070s	415.754us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.570s	574.623us	20	20	100.00
		otp_ctrl_csr_aliasing	6.660s	410.575us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.480s	60.679us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.500s	500.242us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.960s	319.373us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.650s	3.040ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	49.700s	22.630ms	10	10	100.00
		otp_ctrl_check_fail	1.468m	9.489ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.970s	1.260ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	56.250s	8.360ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	51.220s	5.383ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	33.000s	1.346ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.027m	18.171ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.871m	15.396ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.078m	32.435ms	48	50	96.00
V2	stress_all	otp_ctrl_stress_all	17.481m	101.461ms	49	50	98.00
V2	intr_test	otp_ctrl_intr_test	2.370s	553.137us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.440s	279.485us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.890s	387.377us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.890s	387.377us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.830s	1.046ms	5	5	100.00
		otp_ctrl_csr_rw	2.570s	574.623us	20	20	100.00
		otp_ctrl_csr_aliasing	6.660s	410.575us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.910s	543.985us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.830s	1.046ms	5	5	100.00
		otp_ctrl_csr_rw	2.570s	574.623us	20	20	100.00
		otp_ctrl_csr_aliasing	6.660s	410.575us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.910s	543.985us	20	20	100.00
V2		TOTAL			1098	1101	99.73
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
		otp_ctrl_tl_intg_err	49.630s	20.279ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	49.630s	20.279ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	47.360s	7.587ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	47.360s	7.587ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
		otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
		otp_ctrl_macro_errs	1.871m	15.396ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
		otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
		otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
		otp_ctrl_macro_errs	1.871m	15.396ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	1.040m	21.595ms	200	200	100.00
		otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.650s	3.040ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.468m	9.489ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	56.250s	8.360ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	56.250s	8.360ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	56.250s	8.360ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	56.250s	8.360ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	56.250s	8.360ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	47.360s	7.587ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	56.250s	8.360ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	47.360s	7.587ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.529m	154.587ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.970s	1.260ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	47.360s	7.587ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	47.360s	7.587ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.871m	15.396ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.080s	3.435ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.170h	390.500ms	77	100	77.00
V3		TOTAL			78	101	77.23
		TOTAL			1317	1343	98.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.07	93.97	96.69	95.73	92.12	97.51	96.26	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 12 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 12 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.90899385914501238896318829935416602091994889726234436273863304018506253037667
    Line 394, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 149010915 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3538498263 [0xd2e932d7] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 149010915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otp_ctrl_stress_all_with_rand_reset.104781163236896162058060770721330031596127145119623426547618146923073858418672
    Line 38822, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 163042804802 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1667463575 [0x63637997] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 163042804802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.88166912390093431942889897764708501798692883624082479014828306114101181338088
    Line 85092, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 70711549026 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 70711549026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.otp_ctrl_stress_all_with_rand_reset.14220547590079863363592693320614143833247822143320642903832530599684542789170
    Line 19297, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 766366175227 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 766366175227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 72.otp_ctrl_stress_all_with_rand_reset.96558165794851741920780255226025366449005762666932013766539979551298653016043
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  27293042 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  27293042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 77.otp_ctrl_stress_all_with_rand_reset.113819187489025351394306476291917734896974881190967280724345622922497852363130
    Line 38629, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 9257337234 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 9257337234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@283821) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

22.otp_ctrl_test_access.65186105244019420565184960850546823934851235376347006791111732539541756419345
Line 17376, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 518660456 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@283821) { a_addr: 'hc2fba008  a_data: 'h7d644594  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h42  a_opcode: 'h0  a_user: 'h26fba  d_param: 'h0  d_source: 'h42  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 518660456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@348323) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_test_access has 1 failures.

27.otp_ctrl_test_access.76525196657628750196566999982844836318271304099354514816615493159156230994652
Line 20701, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest/run.log

  UVM_ERROR @ 2601973880 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@348323) { a_addr: 'h1179024  a_data: 'h42a10805  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hac  a_opcode: 'h1  a_user: 'h240fa  d_param: 'h0  d_source: 'hac  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 2601973880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otp_ctrl_scoreboard.sv:1677) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@956995) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test otp_ctrl_stress_all has 1 failures.

37.otp_ctrl_stress_all.19590231987815948196760630340537872524775899061854512046843824782073348438219
Line 54634, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2098677719 ps: (otp_ctrl_scoreboard.sv:1677) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface otp_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@956995) { a_addr: 'ha2b1193c  a_data: 'hd010c081  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h0  a_user: 'h24758  d_param: 'h0  d_source: 'hc  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , access gated by lc_dft_en_i
  UVM_INFO @ 2098677719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:827) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.otp_ctrl_stress_all_with_rand_reset.21192550351522938815591330455865363918107711576991658991593451037618496846970
    Line 89030, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 250844703424 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 250844703424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

42.otp_ctrl_stress_all_with_rand_reset.23352775327295117181356025595352004057170768323453263737732607103578570740258
Line 4397, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2318499568 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2319019568 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2319139568 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2320379568 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2320779568 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1