e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | otp_ctrl_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | otp_ctrl_csr_hw_reset | 2.560s | 193.354us | 5 | 5 | 100.00 |
| V1 | csr_rw | otp_ctrl_csr_rw | 2.780s | 679.889us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | otp_ctrl_csr_bit_bash | 10.030s | 791.110us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | otp_ctrl_csr_aliasing | 6.400s | 273.932us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | otp_ctrl_csr_mem_rw_with_rand_reset | 5.720s | 1.723ms | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | otp_ctrl_csr_rw | 2.780s | 679.889us | 20 | 20 | 100.00 |
| otp_ctrl_csr_aliasing | 6.400s | 273.932us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | otp_ctrl_mem_walk | 1.470s | 74.862us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | otp_ctrl_mem_partial_access | 1.450s | 70.431us | 5 | 5 | 100.00 |
| V1 | TOTAL | 64 | 116 | 55.17 | |||
| V2 | dai_access_partition_walk | otp_ctrl_partition_walk | 0 | 1 | 0.00 | ||
| V2 | init_fail | otp_ctrl_init_fail | 0 | 300 | 0.00 | ||
| V2 | partition_check | otp_ctrl_background_chks | 0 | 10 | 0.00 | ||
| otp_ctrl_check_fail | 0 | 50 | 0.00 | ||||
| V2 | regwen_during_otp_init | otp_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2 | partition_lock | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2 | interface_key_check | otp_ctrl_parallel_key_req | 0 | 50 | 0.00 | ||
| V2 | lc_interactions | otp_ctrl_parallel_lc_req | 0 | 50 | 0.00 | ||
| otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||||
| V2 | otp_dai_errors | otp_ctrl_dai_errs | 0 | 50 | 0.00 | ||
| V2 | otp_macro_errors | otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||
| V2 | test_access | otp_ctrl_test_access | 0 | 50 | 0.00 | ||
| V2 | stress_all | otp_ctrl_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | otp_ctrl_intr_test | 2.110s | 577.076us | 50 | 50 | 100.00 |
| V2 | alert_test | otp_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | otp_ctrl_tl_errors | 6.460s | 449.212us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | otp_ctrl_tl_errors | 6.460s | 449.212us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | otp_ctrl_csr_hw_reset | 2.560s | 193.354us | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.780s | 679.889us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 6.400s | 273.932us | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 3.690s | 460.925us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | otp_ctrl_csr_hw_reset | 2.560s | 193.354us | 5 | 5 | 100.00 |
| otp_ctrl_csr_rw | 2.780s | 679.889us | 20 | 20 | 100.00 | ||
| otp_ctrl_csr_aliasing | 6.400s | 273.932us | 5 | 5 | 100.00 | ||
| otp_ctrl_same_csr_outstanding | 3.690s | 460.925us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 1101 | 8.17 | |||
| V2S | sec_cm_additional_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | tl_intg_err | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| otp_ctrl_tl_intg_err | 24.310s | 19.605ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | prim_fsm_check | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_bus_integrity | otp_ctrl_tl_intg_err | 24.310s | 19.605ms | 20 | 20 | 100.00 |
| V2S | sec_cm_secret_mem_scramble | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_digest | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_dai_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_lci_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_part_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scrmbl_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_dai_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_seed_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_kdi_entropy_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_lci_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_part_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_scrmbl_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_integ_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_cnsty_ctr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_timer_lfsr_redun | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_dai_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_lci_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_part_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_scrmbl_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_timer_fsm_local_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_dai_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_lci_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_kdi_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_part_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_scrmbl_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| V2S | sec_cm_timer_fsm_global_esc | otp_ctrl_parallel_lc_esc | 0 | 200 | 0.00 | ||
| otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_part_data_reg_integrity | otp_ctrl_init_fail | 0 | 300 | 0.00 | ||
| V2S | sec_cm_part_data_reg_bkgn_chk | otp_ctrl_check_fail | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_regren | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_sw_unreadable | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_part_mem_sw_unwritable | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_part_mem_sw_noaccess | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_access_ctrl_mubi | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_token_valid_ctrl_mubi | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | otp_ctrl_dai_lock | 0 | 50 | 0.00 | ||
| V2S | sec_cm_test_bus_lc_gated | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_test_tl_lc_gate_fsm_sparse | otp_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_direct_access_config_regwen | otp_ctrl_regwen | 0 | 50 | 0.00 | ||
| V2S | sec_cm_check_trigger_config_regwen | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_check_config_regwen | otp_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_macro_mem_integrity | otp_ctrl_macro_errs | 0 | 50 | 0.00 | ||
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | otp_ctrl_low_freq_read | otp_ctrl_low_freq_read | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | otp_ctrl_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| V3 | TOTAL | 0 | 101 | 0.00 | |||
| TOTAL | 174 | 1343 | 12.96 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 6 | 66.67 |
| V2 | 17 | 17 | 3 | 17.65 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 32.54 | 21.48 | 30.76 | 13.06 | 0.00 | 21.87 | 99.69 | 40.96 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 584 failures:
Test otp_ctrl_wake_up has 1 failures.
Test otp_ctrl_partition_walk has 1 failures.
Test otp_ctrl_init_fail has 183 failures.
0.otp_ctrl_init_fail.85962225283140199447873877974438656151900079733225008732677198050017727707308
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest/run.log
1.otp_ctrl_init_fail.66274732352279334717271528039903740478956668700895672389902386511386209817703
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest/run.log
... and 181 more failures.
Test otp_ctrl_parallel_lc_req has 48 failures.
0.otp_ctrl_parallel_lc_req.8063381621450045190393526307729084986369709546533718329612600613908254011326
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest/run.log
1.otp_ctrl_parallel_lc_req.97737597188950367901322252621368379994180864320243990282666373987631262047854
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest/run.log
... and 46 more failures.
Test otp_ctrl_dai_lock has 48 failures.
0.otp_ctrl_dai_lock.77632381571662343890492825338821450406191202838733760739222608891719832588064
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest/run.log
1.otp_ctrl_dai_lock.5214412214025612382693081851932603949435488568199848584984975279215577082103
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest/run.log
... and 46 more failures.
... and 12 more tests.
Job killed most likely because its dependent job failed. has 584 failures:
Test otp_ctrl_smoke has 8 failures.
0.otp_ctrl_smoke.10520175366433543462751592987322420401521965545574597494087390149864105335940
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest/run.log
1.otp_ctrl_smoke.49352946764436939357347933337055051886780022141061454549091900841947997584589
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest/run.log
... and 6 more failures.
Test otp_ctrl_low_freq_read has 1 failures.
Test otp_ctrl_background_chks has 8 failures.
0.otp_ctrl_background_chks.101530845823657593059986981737523078335928640658560201755560597329503583221979
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest/run.log
1.otp_ctrl_background_chks.63204778222801749266606681801912213169872747513595562173484786748095694433807
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest/run.log
... and 6 more failures.
Test otp_ctrl_parallel_lc_esc has 173 failures.
0.otp_ctrl_parallel_lc_esc.13729092185205779288495834875791854994471166131764307791207457044640959026486
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest/run.log
1.otp_ctrl_parallel_lc_esc.40255336093279528148594452306062816056415421961174760561439046466854652420419
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest/run.log
... and 171 more failures.
Test otp_ctrl_dai_errs has 48 failures.
0.otp_ctrl_dai_errs.104168053037582002657700440839757868467247899173757524864521544617494460883034
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest/run.log
1.otp_ctrl_dai_errs.78357012277420050545232593808869805463060252158755055627123858540898528064795
Log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest/run.log
... and 46 more failures.
... and 12 more tests.
Offending '(cio_test_en_o == *)' has 1 failures:
3.otp_ctrl_csr_mem_rw_with_rand_reset.18076322709316295881905334612638032989921938289106686854581546969339636529633
Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
Offending '(cio_test_en_o == 0)'
UVM_ERROR @ 119992366 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 119992366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---