OTP_CTRL Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.950s	204.217us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.960s	1.848ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.130s	1.453ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.200s	695.497us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.490s	6.806ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.090s	155.424us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.310s	214.739us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.200s	695.497us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	155.424us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.700s	504.796us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.580s	137.153us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.140s	995.197us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.170s	2.397ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	57.280s	28.800ms	10	10	100.00
		otp_ctrl_check_fail	50.930s	6.660ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.480s	1.201ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.271m	8.046ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	43.770s	14.732ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	34.390s	11.774ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.004m	23.781ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.086m	27.813ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.502m	24.038ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	11.905m	88.149ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.160s	633.007us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.240s	914.251us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.780s	1.182ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.780s	1.182ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.130s	1.453ms	5	5	100.00
		otp_ctrl_csr_rw	2.200s	695.497us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	155.424us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.960s	152.625us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.130s	1.453ms	5	5	100.00
		otp_ctrl_csr_rw	2.200s	695.497us	20	20	100.00
		otp_ctrl_csr_aliasing	6.090s	155.424us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.960s	152.625us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
		otp_ctrl_tl_intg_err	42.600s	18.971ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	42.600s	18.971ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.960s	1.848ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.960s	1.848ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
		otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
		otp_ctrl_macro_errs	1.086m	27.813ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
		otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
		otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
		otp_ctrl_macro_errs	1.086m	27.813ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	56.180s	20.968ms	200	200	100.00
		otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.170s	2.397ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	50.930s	6.660ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.271m	8.046ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.271m	8.046ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.271m	8.046ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.271m	8.046ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.271m	8.046ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.960s	1.848ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.271m	8.046ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.960s	1.848ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.783m	15.267ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.480s	1.201ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.960s	1.848ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.960s	1.848ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.086m	27.813ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.550s	3.029ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.190h	1.446s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1326	1343	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.07	93.95	96.69	95.68	92.12	97.46	96.33	93.28

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.61387679970081150634675820846278652806169872569200935363753818383120546582374
      Line 9074, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7818954246 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 7818954246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 24.otp_ctrl_stress_all_with_rand_reset.66915464713764434709724825393551015440726014105055922190001414939665469869680
      Line 12256, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5546157526 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 5546157526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 42.otp_ctrl_stress_all_with_rand_reset.46242818107504916628298963763486239233669552057997317709068909623143910214477
      Line 1615, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11533827018 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (445637701 [0x1a8fe445] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 11533827018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 67.otp_ctrl_stress_all_with_rand_reset.76859512174219962582859920754081628581220259513187341023848871389745280519487
      Line 65029, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 160422365920 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4178322320 [0xf90c2390] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 160422365920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• Offending '(cio_test_en_o == *)' has 3 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

    • 38.otp_ctrl_stress_all_with_rand_reset.78461645446324175096093458520433248097201011372309982432955496904169764054984
      Line 56963, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 175140221584 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 175140221584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 41.otp_ctrl_stress_all_with_rand_reset.24805276373600738289458883238764014640207651439377281637509586780809945739425
      Line 5904, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 16633909607 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 16633909607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 80.otp_ctrl_stress_all_with_rand_reset.101235385936092731240499257381589875487049782294879867509589131048861703714023
      Line 12593, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69747728005 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3382704353 [0xc99ff8e1]) dai addr 760 rdata0 readout mismatch
        UVM_INFO @ 69747728005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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