OTP_CTRL Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: `f7fc348358`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.700s	115.734us	1	1	100.00
V1	smoke	otp_ctrl_smoke	50.010s	5.980ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.480s	236.739us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.430s	623.779us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.180s	1.946ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.110s	1.817ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.620s	161.550us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.430s	623.779us	20	20	100.00
		otp_ctrl_csr_aliasing	6.110s	1.817ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.560s	36.409us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.740s	504.341us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.780s	1.220ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.320s	2.614ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.660s	12.445ms	10	10	100.00
		otp_ctrl_check_fail	50.480s	7.828ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.320s	4.381ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.018m	22.437ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	52.740s	2.299ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	38.340s	12.699ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.349m	26.910ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.020m	6.217ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	52.410s	18.648ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.498m	39.421ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.290s	565.878us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.790s	701.149us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.400s	790.409us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.400s	790.409us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.480s	236.739us	5	5	100.00
		otp_ctrl_csr_rw	2.430s	623.779us	20	20	100.00
		otp_ctrl_csr_aliasing	6.110s	1.817ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.730s	1.504ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.480s	236.739us	5	5	100.00
		otp_ctrl_csr_rw	2.430s	623.779us	20	20	100.00
		otp_ctrl_csr_aliasing	6.110s	1.817ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.730s	1.504ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.160s	18.997ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.160s	18.997ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	50.010s	5.980ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	50.010s	5.980ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
		otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
		otp_ctrl_macro_errs	1.020m	6.217ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
		otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
		otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
		otp_ctrl_macro_errs	1.020m	6.217ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	40.240s	12.627ms	200	200	100.00
		otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.320s	2.614ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	50.480s	7.828ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.018m	22.437ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.018m	22.437ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.018m	22.437ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.018m	22.437ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.018m	22.437ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	50.010s	5.980ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.018m	22.437ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	50.010s	5.980ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.369m	170.112ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.320s	4.381ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	50.010s	5.980ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	50.010s	5.980ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.020m	6.217ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.080s	3.003ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.243h	1.500s	80	100	80.00
V3		TOTAL			81	101	80.20
		TOTAL			1323	1343	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.08	93.97	96.71	95.83	91.89	97.51	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 23.otp_ctrl_stress_all_with_rand_reset.114683645338354471002923416840778585368935125978923983384517502896379257847909
    Line 573, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 123994317963 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 123994317963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.otp_ctrl_stress_all_with_rand_reset.95110837782558903849065358409519205788282640341852214338651202197123819699389
    Line 49083, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 212590288093 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 212590288093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.4344031768554183849586792523022940919893337765986149919023196286267607844477
    Line 16228, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 32571789829 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (79907483 [0x4c34a9b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 32571789829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.otp_ctrl_stress_all_with_rand_reset.51037416428141393165974672643521899228617283886953340147483367332679272129768
    Line 55370, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 601864435321 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4112074223 [0xf51945ef] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 601864435321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.48314043926505059467369172809097969067340547572879312628776943451486776391215
    Line 268, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1910465582 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1068 [0x42c]) dai addr 42c rdata0 readout mismatch
  UVM_INFO @ 1910465582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

46.otp_ctrl_stress_all_with_rand_reset.8184703842034763459063165037234628085020001876004338667918046625858167689333
Line 41161, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 303694421651 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 303695588320 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 303700088329 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 303701088331 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 303704755005 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 52.otp_ctrl_stress_all_with_rand_reset.42331788454165693343688570507184211671852255006663755343392532516286469602674
    Line 18954, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 929658016746 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 929658016746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```