OTP_CTRL Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: `e3ca274e77`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.880s	199.236us	1	1	100.00
V1	smoke	otp_ctrl_smoke	1.528m	10.498ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.500s	215.597us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.200s	545.793us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	7.570s	496.235us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.860s	747.531us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.150s	1.674ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.200s	545.793us	20	20	100.00
		otp_ctrl_csr_aliasing	6.860s	747.531us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.440s	65.476us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.440s	73.066us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	24.330s	5.099ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.800s	2.558ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	31.600s	3.302ms	10	10	100.00
		otp_ctrl_check_fail	47.440s	5.982ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	11.720s	4.084ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	53.440s	5.209ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.017m	3.496ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.410s	9.904ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.140m	24.611ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	5.020m	32.332ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.151m	33.591ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.000m	29.065ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.070s	569.364us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.540s	879.873us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.340s	1.196ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.340s	1.196ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.500s	215.597us	5	5	100.00
		otp_ctrl_csr_rw	2.200s	545.793us	20	20	100.00
		otp_ctrl_csr_aliasing	6.860s	747.531us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.850s	141.501us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.500s	215.597us	5	5	100.00
		otp_ctrl_csr_rw	2.200s	545.793us	20	20	100.00
		otp_ctrl_csr_aliasing	6.860s	747.531us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.850s	141.501us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
		otp_ctrl_tl_intg_err	31.850s	19.808ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	31.850s	19.808ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	1.528m	10.498ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	1.528m	10.498ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
		otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
		otp_ctrl_macro_errs	5.020m	32.332ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
		otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
		otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
		otp_ctrl_macro_errs	5.020m	32.332ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.370s	11.260ms	200	200	100.00
		otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.800s	2.558ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	47.440s	5.982ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	53.440s	5.209ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	53.440s	5.209ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	53.440s	5.209ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	53.440s	5.209ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	53.440s	5.209ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	1.528m	10.498ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	53.440s	5.209ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	1.528m	10.498ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.845m	12.976ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	11.720s	4.084ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	1.528m	10.498ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	1.528m	10.498ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	5.020m	32.332ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.520s	5.880ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.605h	2.483s	87	100	87.00
V3		TOTAL			88	101	87.13
		TOTAL			1329	1343	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.13	93.99	96.66	95.89	92.12	97.56	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.40695448736630135166925344519220260125240895983805340014874584373115799740185
    Line 5353, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28334321502 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1906687483 [0x71a5bdfb] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 28334321502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otp_ctrl_stress_all_with_rand_reset.45578874592704215098948214627004142893145163100334420635932076097331127459715
    Line 20163, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 299241238924 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (393646484 [0x17769194] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 299241238924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 13.otp_ctrl_stress_all_with_rand_reset.98008065665077761006047669518406300998376658668467356410151361085688531661445
    Line 54888, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 833575190935 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 833575190935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.otp_ctrl_stress_all_with_rand_reset.86170185263008598180209009866973841105783578416330217898115371419349905262628
    Line 4129, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 838822795 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 838822795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.otp_ctrl_csr_mem_rw_with_rand_reset.86678616490294755544179641287407175757623467854166715884660356986128884064660
    Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  53093757 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  53093757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.21660138204057629832956783722127365794128383309329357203630310375393428042684
    Line 51891, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 560342256836 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 560342256836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

42.otp_ctrl_stress_all_with_rand_reset.25826131072926420243475870684473120526770283542297497732833645040477958415153
Line 9094, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 254421134280 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 254421414280 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 254421494280 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 254422174280 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 254422334280 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

91.otp_ctrl_stress_all_with_rand_reset.105506615966535405097153713345442347249392820293128010238490118368120437862963
Line 45640, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 56685240656 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 56685293286 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 56685303812 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 56685556436 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 56685566962 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 4.otp_ctrl_stress_all_with_rand_reset.38845908324528504463811530101883964200553216534751999072212336661730433854591
    Line 55767, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46594341245 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1568221125 [0x5d7927c5]) dai addr 714 rdata0 readout mismatch
  UVM_INFO @ 46594341245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```