OTP_CTRL Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.810s	91.621us	1	1	100.00
V1	smoke	otp_ctrl_smoke	19.230s	1.619ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.680s	396.962us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.090s	562.986us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	16.520s	6.761ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.700s	568.285us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.710s	1.791ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.090s	562.986us	20	20	100.00
		otp_ctrl_csr_aliasing	6.700s	568.285us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.850s	535.071us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.620s	545.393us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.190s	312.858us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.100s	2.679ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	38.920s	3.408ms	10	10	100.00
		otp_ctrl_check_fail	54.530s	26.526ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.310s	4.966ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	49.410s	2.315ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	47.950s	16.939ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	31.100s	12.187ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	48.080s	1.464ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.666m	12.348ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.257m	34.209ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.098m	169.330ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.450s	611.050us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.140s	167.617us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.230s	2.335ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.230s	2.335ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.680s	396.962us	5	5	100.00
		otp_ctrl_csr_rw	2.090s	562.986us	20	20	100.00
		otp_ctrl_csr_aliasing	6.700s	568.285us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.190s	1.460ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.680s	396.962us	5	5	100.00
		otp_ctrl_csr_rw	2.090s	562.986us	20	20	100.00
		otp_ctrl_csr_aliasing	6.700s	568.285us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.190s	1.460ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
		otp_ctrl_tl_intg_err	44.190s	20.224ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	44.190s	20.224ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	19.230s	1.619ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	19.230s	1.619ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
		otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
		otp_ctrl_macro_errs	1.666m	12.348ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
		otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
		otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
		otp_ctrl_macro_errs	1.666m	12.348ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.510s	16.889ms	200	200	100.00
		otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.100s	2.679ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	54.530s	26.526ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	49.410s	2.315ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	49.410s	2.315ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	49.410s	2.315ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	49.410s	2.315ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	49.410s	2.315ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	19.230s	1.619ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	49.410s	2.315ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	19.230s	1.619ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.477m	14.250ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.310s	4.966ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	19.230s	1.619ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	19.230s	1.619ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.666m	12.348ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	27.700s	7.555ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.224h	1.761s	79	100	79.00
V3		TOTAL			80	101	79.21
		TOTAL			1322	1343	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.95	93.86	96.44	95.50	92.36	97.00	96.26	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 14.otp_ctrl_stress_all_with_rand_reset.48296220537505082492030307289816379757768875162155233930828759057755976876008
    Line 407, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 55558089707 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 55558089707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.otp_ctrl_stress_all_with_rand_reset.61053112106968155935239393238780512017101991399059886390712818790396780111372
    Line 29547, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1291638744301 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1291638744301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.23294237085403481177449928264528326467754087785503333060527660617911535296596
    Line 14990, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 156281612989 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4170350183 [0xf8927e67] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 156281612989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.otp_ctrl_stress_all_with_rand_reset.55687593744592899243163103046273128336537587489859882126197107853736450311612
    Line 66471, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 67594159532 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1346407404 [0x50408bec] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 67594159532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 25.otp_ctrl_stress_all_with_rand_reset.46004475031673163838234242727496992372736979982978246249225056617664084137245
    Line 102722, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 57504170963 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 57504170963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 28.otp_ctrl_stress_all_with_rand_reset.35296127427010313506996446392631126997711130278159757610609087301814308544337
    Line 81610, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 53233353315 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 53233353315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

19.otp_ctrl_stress_all_with_rand_reset.12019659277590471411475928384074635736234838971881807008695235276472484695821
Line 3586, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2541174011 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2541334011 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2541424011 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2541704011 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2541784011 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

73.otp_ctrl_stress_all_with_rand_reset.4949859963700712611851302293523084166058615851774461955449391642447909442645
Line 38566, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 879157580254 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 879157809417 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 879157892749 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 879159038564 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 879159101063 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.otp_ctrl_stress_all_with_rand_reset.27683897831236308325678116857399201994976770317301567060410816651031917944087
    Line 48371, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 609057290595 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 609057290595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 95.otp_ctrl_stress_all_with_rand_reset.35721499374958028234488462836031087492439409292739856909050457929381595663388
    Line 14150, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26021747478 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1340 [0x53c]) dai addr 53c rdata0 readout mismatch
  UVM_INFO @ 26021747478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```