OTP_CTRL Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.660s	57.350us	1	1	100.00
V1	smoke	otp_ctrl_smoke	21.300s	1.852ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.450s	207.337us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.190s	672.403us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.640s	7.527ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.560s	751.034us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.990s	159.039us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.190s	672.403us	20	20	100.00
		otp_ctrl_csr_aliasing	6.560s	751.034us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.460s	71.886us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.450s	144.901us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.950s	803.241us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.550s	2.083ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	32.850s	13.641ms	10	10	100.00
		otp_ctrl_check_fail	58.610s	19.843ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.020s	4.751ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	41.840s	17.540ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	45.140s	2.137ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	40.660s	11.980ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.305m	24.978ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	56.350s	18.671ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.453m	9.008ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.954m	128.756ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.130s	590.474us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.040s	905.264us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.420s	3.125ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.420s	3.125ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.450s	207.337us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	672.403us	20	20	100.00
		otp_ctrl_csr_aliasing	6.560s	751.034us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.770s	1.855ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.450s	207.337us	5	5	100.00
		otp_ctrl_csr_rw	2.190s	672.403us	20	20	100.00
		otp_ctrl_csr_aliasing	6.560s	751.034us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.770s	1.855ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.470s	19.878ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.470s	19.878ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	21.300s	1.852ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	21.300s	1.852ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
		otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
		otp_ctrl_macro_errs	56.350s	18.671ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
		otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
		otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
		otp_ctrl_macro_errs	56.350s	18.671ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.110s	13.212ms	200	200	100.00
		otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.550s	2.083ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	58.610s	19.843ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	41.840s	17.540ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	41.840s	17.540ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	41.840s	17.540ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	41.840s	17.540ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	41.840s	17.540ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	21.300s	1.852ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	41.840s	17.540ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	21.300s	1.852ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.270m	169.470ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.020s	4.751ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	21.300s	1.852ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	21.300s	1.852ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	56.350s	18.671ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.840s	3.063ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	58.712m	350.064ms	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	93.88	96.77	95.80	91.41	96.95	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 11.otp_ctrl_stress_all_with_rand_reset.2868971802363580158951572979698364620875664425633305692509396096781452474103
    Line 22835, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 48895908923 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 48895908923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.otp_ctrl_stress_all_with_rand_reset.96950514885488763989445002760042084752381605380448990630940884202849284524771
    Line 80687, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 138626678049 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 138626678049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 30.otp_ctrl_stress_all_with_rand_reset.93899429571655992131813476623423513580713445757610786975537810795191010695565
    Line 34795, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6797599037 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3610597003 [0xd735568b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 6797599037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.otp_ctrl_stress_all_with_rand_reset.30924289349026120611885435466724787732434803890231632741112734006421950288337
    Line 3111, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 162899641538 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3793314097 [0xe2196131] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 162899641538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed

has 3 failures:

Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

0.otp_ctrl_stress_all_with_rand_reset.112841106578293514757432935486355626209331401995580915368574756751846863610979
Line 13827, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 84403836120 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 84404305504 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 84404325912 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 84405040192 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 84405060600 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

27.otp_ctrl_stress_all_with_rand_reset.98656531332701352329814449018603773771658406682801468657138879310248648675610
Line 35068, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 110851569579 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 110852402899 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 110852423732 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 110853486215 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 110853507048 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

... and 1 more failures.

Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.90098379674022911190102317229734706038653723521144582181998274974529509883891
    Line 47039, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 739791962321 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 739791962321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.otp_ctrl_stress_all_with_rand_reset.25481857280055479283287751433681633986748063456452788309253102548054120021742
    Line 16952, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 84192786555 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 84192786555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```