OTP_CTRL Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.820s	111.718us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.770s	3.288ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.240s	1.401ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.300s	663.003us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.330s	970.254us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.040s	382.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.700s	1.582ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.300s	663.003us	20	20	100.00
		otp_ctrl_csr_aliasing	7.040s	382.565us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.400s	517.453us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.630s	502.589us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	21.260s	5.073ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.420s	3.117ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	54.330s	6.653ms	10	10	100.00
		otp_ctrl_check_fail	44.510s	25.753ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	16.380s	4.778ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.142m	6.432ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	44.930s	6.039ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	47.750s	12.238ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	54.240s	17.514ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.471m	17.078ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	2.329m	15.891ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.028m	105.761ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.220s	582.832us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.570s	1.071ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.820s	2.343ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.820s	2.343ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.240s	1.401ms	5	5	100.00
		otp_ctrl_csr_rw	2.300s	663.003us	20	20	100.00
		otp_ctrl_csr_aliasing	7.040s	382.565us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.870s	243.706us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.240s	1.401ms	5	5	100.00
		otp_ctrl_csr_rw	2.300s	663.003us	20	20	100.00
		otp_ctrl_csr_aliasing	7.040s	382.565us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.870s	243.706us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
		otp_ctrl_tl_intg_err	25.460s	2.308ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	25.460s	2.308ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.770s	3.288ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.770s	3.288ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
		otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
		otp_ctrl_macro_errs	2.471m	17.078ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
		otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
		otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
		otp_ctrl_macro_errs	2.471m	17.078ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.330s	4.212ms	200	200	100.00
		otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.420s	3.117ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	44.510s	25.753ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.142m	6.432ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.142m	6.432ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.142m	6.432ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.142m	6.432ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.142m	6.432ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.770s	3.288ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.142m	6.432ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.770s	3.288ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.229m	182.489ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	16.380s	4.778ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.770s	3.288ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.770s	3.288ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.471m	17.078ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	18.400s	5.948ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.663h	2.208s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.84	96.70	95.84	91.17	97.14	96.33	93.14

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 28.otp_ctrl_stress_all_with_rand_reset.84714733426493245327980439812786081537157461682206048919111781309774402155983
      Line 26421, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 619390186995 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 619390186995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.otp_ctrl_stress_all_with_rand_reset.23883977423966936236496867457160248788176763809908013699993015296670728005877
      Line 104421, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 414174972925 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 414174972925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 49.otp_ctrl_stress_all_with_rand_reset.32460862846436357747254851365914600889171036663105548344752145506042536234111
      Line 334, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 119026498 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1288147712 [0x4cc79300] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 119026498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 51.otp_ctrl_stress_all_with_rand_reset.82533538479657212195735414385862294960280524459432764313203576401316123825503
      Line 69847, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1227074714113 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1720834683 [0x6691da7b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 1227074714113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• Offending '(cio_test_en_o == *)' has 4 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.

    • 13.otp_ctrl_csr_mem_rw_with_rand_reset.110487698305967408150362618258294285456781789929171402424482622339889129719291
      Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 228476322 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 228476322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 17.otp_ctrl_csr_mem_rw_with_rand_reset.81514468891847458106700906435425034088507900665602078816421193999184387978093
      Line 267, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 108342642 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 108342642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 65.otp_ctrl_stress_all_with_rand_reset.102536755966849291434117421748349556940557928964679988851495394449412209412676
      Line 59634, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 956836979046 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 956836979046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 67.otp_ctrl_stress_all_with_rand_reset.106641960535567456975715919776409472577610190506118345673798301002061586540408
      Line 376, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 22876360036 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 22876360036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 12.otp_ctrl_stress_all_with_rand_reset.114794921231787900005986169560630164954178571026352591991530449473275139552475
      Line 75727, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 118538755833 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1172 [0x494]) dai addr 494 rdata0 readout mismatch
        UVM_INFO @ 118538755833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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