OTP_CTRL Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 1.660s 52.438us 1 1 100.00
V1 smoke otp_ctrl_smoke 14.540s 6.761ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 4.560s 1.461ms 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.470s 588.361us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 12.310s 6.750ms 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 6.870s 1.842ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 4.160s 1.570ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.470s 588.361us 20 20 100.00
otp_ctrl_csr_aliasing 6.870s 1.842ms 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.870s 521.311us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.600s 563.722us 5 5 100.00
V1 TOTAL 116 116 100.00
V2 dai_access_partition_walk otp_ctrl_partition_walk 19.600s 643.262us 1 1 100.00
V2 init_fail otp_ctrl_init_fail 7.400s 2.702ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 44.230s 23.968ms 10 10 100.00
otp_ctrl_check_fail 2.309m 22.750ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 12.940s 354.190us 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 43.570s 22.881ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 47.470s 2.024ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 39.430s 15.045ms 50 50 100.00
otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
V2 otp_dai_errors otp_ctrl_dai_errs 59.140s 6.784ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 58.320s 4.654ms 50 50 100.00
V2 test_access otp_ctrl_test_access 59.720s 26.608ms 50 50 100.00
V2 stress_all otp_ctrl_stress_all 6.040m 105.411ms 50 50 100.00
V2 intr_test otp_ctrl_intr_test 2.320s 621.629us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 5.340s 555.241us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 7.460s 669.430us 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 7.460s 669.430us 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 4.560s 1.461ms 5 5 100.00
otp_ctrl_csr_rw 2.470s 588.361us 20 20 100.00
otp_ctrl_csr_aliasing 6.870s 1.842ms 5 5 100.00
otp_ctrl_same_csr_outstanding 3.130s 185.987us 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 4.560s 1.461ms 5 5 100.00
otp_ctrl_csr_rw 2.470s 588.361us 20 20 100.00
otp_ctrl_csr_aliasing 6.870s 1.842ms 5 5 100.00
otp_ctrl_same_csr_outstanding 3.130s 185.987us 20 20 100.00
V2 TOTAL 1100 1101 99.91
V2S sec_cm_additional_check otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
otp_ctrl_tl_intg_err 39.620s 18.922ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 39.620s 18.922ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 14.540s 6.761ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 14.540s 6.761ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
otp_ctrl_macro_errs 58.320s 4.654ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
otp_ctrl_macro_errs 58.320s 4.654ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 34.090s 12.489ms 199 200 99.50
otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 7.400s 2.702ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 2.309m 22.750ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 43.570s 22.881ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 43.570s 22.881ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 43.570s 22.881ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 43.570s 22.881ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 43.570s 22.881ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 14.540s 6.761ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 43.570s 22.881ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 14.540s 6.761ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 3.257m 10.472ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 12.940s 354.190us 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 14.540s 6.761ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 14.540s 6.761ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 58.320s 4.654ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 13.430s 5.899ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 1.191h 2.042s 87 100 87.00
V3 TOTAL 88 101 87.13
TOTAL 1329 1343 98.96

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 17 17 16 94.12
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.05 93.83 96.30 95.68 92.84 97.00 96.33 93.35

Failure Buckets

Past Results