OTP_CTRL Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.660s	52.438us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.540s	6.761ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.560s	1.461ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.470s	588.361us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	12.310s	6.750ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.870s	1.842ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.160s	1.570ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.470s	588.361us	20	20	100.00
		otp_ctrl_csr_aliasing	6.870s	1.842ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.870s	521.311us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.600s	563.722us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.600s	643.262us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.400s	2.702ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	44.230s	23.968ms	10	10	100.00
		otp_ctrl_check_fail	2.309m	22.750ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.940s	354.190us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	43.570s	22.881ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	47.470s	2.024ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	39.430s	15.045ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
V2	otp_dai_errors	otp_ctrl_dai_errs	59.140s	6.784ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	58.320s	4.654ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	59.720s	26.608ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.040m	105.411ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.320s	621.629us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.340s	555.241us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.460s	669.430us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.460s	669.430us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.560s	1.461ms	5	5	100.00
		otp_ctrl_csr_rw	2.470s	588.361us	20	20	100.00
		otp_ctrl_csr_aliasing	6.870s	1.842ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.130s	185.987us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.560s	1.461ms	5	5	100.00
		otp_ctrl_csr_rw	2.470s	588.361us	20	20	100.00
		otp_ctrl_csr_aliasing	6.870s	1.842ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.130s	185.987us	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
		otp_ctrl_tl_intg_err	39.620s	18.922ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	39.620s	18.922ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.540s	6.761ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.540s	6.761ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
		otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
		otp_ctrl_macro_errs	58.320s	4.654ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
		otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
		otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
		otp_ctrl_macro_errs	58.320s	4.654ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.090s	12.489ms	199	200	99.50
		otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.400s	2.702ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	2.309m	22.750ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	43.570s	22.881ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	43.570s	22.881ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	43.570s	22.881ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	43.570s	22.881ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	43.570s	22.881ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.540s	6.761ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	43.570s	22.881ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.540s	6.761ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.257m	10.472ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.940s	354.190us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.540s	6.761ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.540s	6.761ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	58.320s	4.654ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.430s	5.899ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.191h	2.042s	87	100	87.00
V3		TOTAL			88	101	87.13
		TOTAL			1329	1343	98.96

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.05	93.83	96.30	95.68	92.84	97.00	96.33	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 13.otp_ctrl_stress_all_with_rand_reset.107867805026682942069402081122615165218563016358032894831933687105012163538790
      Line 38547, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 123757646587 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 123757646587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 35.otp_ctrl_stress_all_with_rand_reset.17939398682259664668006954672143597691580195959867528398146278059661612909891
      Line 81027, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66724817192 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 66724817192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 4 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

    • 10.otp_ctrl_stress_all_with_rand_reset.35897612436927806010463863655298959870857371023475211239527032658802462209714
      Line 616, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 197107367 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2068371408 [0x7b48d7d0] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 197107367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.otp_ctrl_stress_all_with_rand_reset.4017846907757212756151278182381117187466658237781853043999144915501296575220
      Line 15769, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 357373857438 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2669964370 [0x9f246c52] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 357373857438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.otp_ctrl_stress_all_with_rand_reset.42148744662895796940834862331450735024998438310582357699045197900635325440850
      Line 31475, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 25839532599 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 25839532599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 45.otp_ctrl_stress_all_with_rand_reset.84872039644709739541355751182559906068001171024146409976996349924447104704700
      Line 7367, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22310585691 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 22310585691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:

  • Test otp_ctrl_parallel_lc_esc has 1 failures.

    • 59.otp_ctrl_parallel_lc_esc.100137416883710746690146308390952289658676927031500359266215239700441006460456
      Line 2099, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest/run.log

        UVM_ERROR @ 114609653 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
        UVM_INFO @ 114609653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 79.otp_ctrl_stress_all_with_rand_reset.919317458106227417819055072841239054586032225568140128270328582853492959015
      Line 44073, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70126601778 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1513986053 [0x5a3d9805]) dai addr 750 rdata0 readout mismatch
        UVM_INFO @ 70126601778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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