OTP_CTRL Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.810s	205.708us	1	1	100.00
V1	smoke	otp_ctrl_smoke	12.870s	4.555ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.500s	376.962us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.030s	563.517us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	15.750s	5.585ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.070s	3.092ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.790s	1.737ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.030s	563.517us	20	20	100.00
		otp_ctrl_csr_aliasing	7.070s	3.092ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.400s	139.485us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.320s	560.684us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	17.980s	313.644us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.110s	2.411ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.103m	7.440ms	10	10	100.00
		otp_ctrl_check_fail	39.950s	2.174ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.070s	398.895us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	47.700s	27.421ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	49.640s	3.911ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	54.000s	14.954ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.085m	19.655ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.158m	27.750ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.119m	6.280ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.859m	14.460ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.140s	610.118us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.140s	805.900us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.470s	390.516us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.470s	390.516us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.500s	376.962us	5	5	100.00
		otp_ctrl_csr_rw	2.030s	563.517us	20	20	100.00
		otp_ctrl_csr_aliasing	7.070s	3.092ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.990s	567.260us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.500s	376.962us	5	5	100.00
		otp_ctrl_csr_rw	2.030s	563.517us	20	20	100.00
		otp_ctrl_csr_aliasing	7.070s	3.092ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.990s	567.260us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
		otp_ctrl_tl_intg_err	23.640s	2.122ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	23.640s	2.122ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	12.870s	4.555ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	12.870s	4.555ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
		otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
		otp_ctrl_macro_errs	1.158m	27.750ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
		otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
		otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
		otp_ctrl_macro_errs	1.158m	27.750ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.040s	12.739ms	200	200	100.00
		otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.110s	2.411ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	39.950s	2.174ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	47.700s	27.421ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	47.700s	27.421ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	47.700s	27.421ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	47.700s	27.421ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	47.700s	27.421ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	12.870s	4.555ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	47.700s	27.421ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	12.870s	4.555ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.414m	173.236ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.070s	398.895us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	12.870s	4.555ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	12.870s	4.555ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.158m	27.750ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.500s	7.491ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.260h	211.661ms	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.82	93.93	96.32	95.58	91.17	97.09	96.33	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 13 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 13 failures.

    • 10.otp_ctrl_stress_all_with_rand_reset.56074060220772374671789804926768845299889795054013134668888846700313837328823
      Line 323, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 102986546 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 102986546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.otp_ctrl_stress_all_with_rand_reset.115505534286610522746252583098269064977310614331596622852528213373606726456182
      Line 3011, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 140477488271 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 140477488271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 11 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 5 failures.

    • 8.otp_ctrl_stress_all_with_rand_reset.114689409888083382572771448002867562760076044505331715284244916301098760517132
      Line 21509, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26254576931 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3580826908 [0xd56f151c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 26254576931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 61.otp_ctrl_stress_all_with_rand_reset.34043797448996165721787403984458022790410781961247727828664346361455915601101
      Line 59197, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 32914246985 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1501409638 [0x597db166] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 32914246985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• Offending '(cio_test_en_o == *)' has 1 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.otp_ctrl_stress_all_with_rand_reset.30264881998668971269400999490680514600852581795802696133992376877717822248383
      Line 12202, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 914806263332 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 914806263332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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