OTP_CTRL Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.900s	163.776us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.710s	8.815ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.170s	1.447ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.900s	564.999us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.580s	843.713us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	4.680s	294.225us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.150s	1.531ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.900s	564.999us	20	20	100.00
		otp_ctrl_csr_aliasing	4.680s	294.225us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.390s	65.451us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.420s	78.634us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.570s	2.412ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.630s	2.399ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	27.880s	1.397ms	10	10	100.00
		otp_ctrl_check_fail	47.900s	6.429ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.400s	4.390ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	39.170s	2.189ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.043m	24.341ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.450s	9.623ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	40.970s	21.290ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	3.072m	23.843ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	42.660s	11.400ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.006m	35.985ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.640s	572.027us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	5.900s	527.224us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.770s	374.868us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.770s	374.868us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.170s	1.447ms	5	5	100.00
		otp_ctrl_csr_rw	1.900s	564.999us	20	20	100.00
		otp_ctrl_csr_aliasing	4.680s	294.225us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.630s	1.030ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.170s	1.447ms	5	5	100.00
		otp_ctrl_csr_rw	1.900s	564.999us	20	20	100.00
		otp_ctrl_csr_aliasing	4.680s	294.225us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.630s	1.030ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.690s	19.843ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.690s	19.843ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.710s	8.815ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.710s	8.815ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
		otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
		otp_ctrl_macro_errs	3.072m	23.843ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
		otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
		otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
		otp_ctrl_macro_errs	3.072m	23.843ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.220s	17.913ms	200	200	100.00
		otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.630s	2.399ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	47.900s	6.429ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	39.170s	2.189ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	39.170s	2.189ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	39.170s	2.189ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	39.170s	2.189ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	39.170s	2.189ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.710s	8.815ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	39.170s	2.189ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.710s	8.815ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.313m	173.023ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.400s	4.390ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.710s	8.815ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.710s	8.815ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	3.072m	23.843ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.780s	3.032ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.924h	2.203s	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.94	93.81	96.72	95.80	91.65	97.14	96.26	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.50907991359670294078431911108913190635153152240118950618109388672441190490057
    Line 4242, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1658319531 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1658319531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.otp_ctrl_stress_all_with_rand_reset.35241873877157356885638212646231455543160999408842769398402338584932956864826
    Line 21625, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 36161129762 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 36161129762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.57898683347833820612768021555633912822965723422909360809103202446816377855788
    Line 29816, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 94174004958 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3497730938 [0xd07b237a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 94174004958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.otp_ctrl_stress_all_with_rand_reset.76759714411909765766958709734015508727528929102384997161396003823887755624137
    Line 544, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15536681580 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1116813672 [0x42913968] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 15536681580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed

has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

17.otp_ctrl_stress_all_with_rand_reset.26940126417369428273790638480422645626617952186750666230398848772313544677529
Line 13898, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 22704593008 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 22704753008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22704793008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22706633008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22706673008 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1