OTP_CTRL Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.760s	56.864us	1	1	100.00
V1	smoke	otp_ctrl_smoke	17.340s	7.177ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.110s	1.544ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.080s	178.814us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.550s	460.924us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.980s	1.648ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.910s	200.270us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.080s	178.814us	20	20	100.00
		otp_ctrl_csr_aliasing	5.980s	1.648ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.770s	552.266us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.400s	66.423us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	23.360s	3.188ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.360s	2.583ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	45.400s	5.004ms	10	10	100.00
		otp_ctrl_check_fail	41.850s	6.493ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.330s	5.789ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	3.562m	24.644ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.141m	3.180ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	41.990s	13.376ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
V2	otp_dai_errors	otp_ctrl_dai_errs	58.800s	25.463ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.011m	5.569ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	49.880s	5.547ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.340m	36.506ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.040s	561.132us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.080s	811.867us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.520s	2.435ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.520s	2.435ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.110s	1.544ms	5	5	100.00
		otp_ctrl_csr_rw	2.080s	178.814us	20	20	100.00
		otp_ctrl_csr_aliasing	5.980s	1.648ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.340s	1.514ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.110s	1.544ms	5	5	100.00
		otp_ctrl_csr_rw	2.080s	178.814us	20	20	100.00
		otp_ctrl_csr_aliasing	5.980s	1.648ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.340s	1.514ms	20	20	100.00
V2		TOTAL			1100	1101	99.91
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
		otp_ctrl_tl_intg_err	25.470s	4.770ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	25.470s	4.770ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	17.340s	7.177ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	17.340s	7.177ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
		otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
		otp_ctrl_macro_errs	1.011m	5.569ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
		otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
		otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
		otp_ctrl_macro_errs	1.011m	5.569ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.420s	4.967ms	199	200	99.50
		otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.360s	2.583ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	41.850s	6.493ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	3.562m	24.644ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	3.562m	24.644ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	3.562m	24.644ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	3.562m	24.644ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	3.562m	24.644ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	17.340s	7.177ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	3.562m	24.644ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	17.340s	7.177ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.373m	173.030ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.330s	5.789ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	17.340s	7.177ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	17.340s	7.177ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.011m	5.569ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	14.130s	5.917ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.667h	2.226s	83	100	83.00
V3		TOTAL			84	101	83.17
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	16	94.12
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.75	96.20	95.73	92.12	96.90	96.33	93.14

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 7 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.73396696059589963344899348676625765755575491917374482278514776002023026487664
    Line 368, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48920481 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1265504175 [0x4b6e0faf] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  48920481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.otp_ctrl_stress_all_with_rand_reset.21168071956754856023290916702668589722051312979717339189053495660645903420971
    Line 10212, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 157004043423 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1583157766 [0x5e5d1206] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 157004043423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 4 failures:

Test otp_ctrl_stress_all_with_rand_reset has 4 failures.

22.otp_ctrl_stress_all_with_rand_reset.75676142876491875971532956226209334411478692585841480373980649483479718580357
Line 42055, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 77454735782 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 77455110785 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 77455152452 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 77456402462 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 77456444129 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

23.otp_ctrl_stress_all_with_rand_reset.8362466130742229447535343569823578042989384436808337565481025081396868011081
Line 111620, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 327955534977 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 327960201653 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 327960868321 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 327963034992 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 327963034992 ps: (dv_base_reg.sv:325) [otp_ctrl_core_reg_block.direct_access_regwen] lock_lockable_flds          0 val

... and 2 more failures.

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 84.otp_ctrl_stress_all_with_rand_reset.59403248820369200478863423819105424940318807802427168950635662914346445680423
    Line 2264, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 559587495 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 559587495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 94.otp_ctrl_stress_all_with_rand_reset.45755539823849259690357336049303390234711837710956718925037165719786674405947
    Line 31574, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 49963039494 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 49963039494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.111596205331672875393521193008576635302565293157331412255218609271129704988423
    Line 18758, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 253828719319 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 249282008 [0xedbbdd8]) dai addr 790 rdata0 readout mismatch
  UVM_INFO @ 253828719319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.otp_ctrl_stress_all_with_rand_reset.85692005594490206482126380191164320898887789035816369234263995713461540379138
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  26924147 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  26924147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 78.otp_ctrl_stress_all_with_rand_reset.49650314146756511958351134892918968133453862710965604294517301436106835763167
    Line 45325, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63652334691 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 28 [0x1c]) dai addr 1c rdata0 readout mismatch
  UVM_INFO @ 63652334691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_check_error did not trigger max_delay:* has 1 failures:
- Test otp_ctrl_parallel_lc_esc has 1 failures.
  - 180.otp_ctrl_parallel_lc_esc.32027376285335872714051286597569010742819821307759514873416010006574222344551
    Line 6379, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest/run.log
```
  UVM_ERROR @ 222139891 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_check_error did not trigger max_delay:5
  UVM_INFO @ 222139891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```