OTP_CTRL Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up otp_ctrl_wake_up 2.260s 752.810us 1 1 100.00
V1 smoke otp_ctrl_smoke 18.620s 6.853ms 50 50 100.00
V1 csr_hw_reset otp_ctrl_csr_hw_reset 3.140s 1.049ms 5 5 100.00
V1 csr_rw otp_ctrl_csr_rw 2.500s 633.213us 20 20 100.00
V1 csr_bit_bash otp_ctrl_csr_bit_bash 11.940s 5.594ms 5 5 100.00
V1 csr_aliasing otp_ctrl_csr_aliasing 6.970s 448.927us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otp_ctrl_csr_mem_rw_with_rand_reset 5.780s 1.720ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otp_ctrl_csr_rw 2.500s 633.213us 20 20 100.00
otp_ctrl_csr_aliasing 6.970s 448.927us 5 5 100.00
V1 mem_walk otp_ctrl_mem_walk 1.460s 563.071us 5 5 100.00
V1 mem_partial_access otp_ctrl_mem_partial_access 1.630s 526.839us 5 5 100.00
V1 TOTAL 116 116 100.00
V2 dai_access_partition_walk otp_ctrl_partition_walk 20.100s 327.222us 1 1 100.00
V2 init_fail otp_ctrl_init_fail 8.720s 3.094ms 300 300 100.00
V2 partition_check otp_ctrl_background_chks 56.180s 34.245ms 10 10 100.00
otp_ctrl_check_fail 33.940s 5.533ms 50 50 100.00
V2 regwen_during_otp_init otp_ctrl_regwen 13.950s 5.237ms 50 50 100.00
V2 partition_lock otp_ctrl_dai_lock 54.150s 9.071ms 50 50 100.00
V2 interface_key_check otp_ctrl_parallel_key_req 1.101m 23.786ms 50 50 100.00
V2 lc_interactions otp_ctrl_parallel_lc_req 32.430s 12.249ms 50 50 100.00
otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
V2 otp_dai_errors otp_ctrl_dai_errs 43.070s 1.767ms 50 50 100.00
V2 otp_macro_errors otp_ctrl_macro_errs 1.178m 5.278ms 50 50 100.00
V2 test_access otp_ctrl_test_access 59.630s 5.764ms 50 50 100.00
V2 stress_all otp_ctrl_stress_all 6.499m 42.569ms 50 50 100.00
V2 intr_test otp_ctrl_intr_test 2.160s 572.681us 50 50 100.00
V2 alert_test otp_ctrl_alert_test 6.160s 813.438us 50 50 100.00
V2 tl_d_oob_addr_access otp_ctrl_tl_errors 9.400s 3.239ms 20 20 100.00
V2 tl_d_illegal_access otp_ctrl_tl_errors 9.400s 3.239ms 20 20 100.00
V2 tl_d_outstanding_access otp_ctrl_csr_hw_reset 3.140s 1.049ms 5 5 100.00
otp_ctrl_csr_rw 2.500s 633.213us 20 20 100.00
otp_ctrl_csr_aliasing 6.970s 448.927us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.730s 133.567us 20 20 100.00
V2 tl_d_partial_access otp_ctrl_csr_hw_reset 3.140s 1.049ms 5 5 100.00
otp_ctrl_csr_rw 2.500s 633.213us 20 20 100.00
otp_ctrl_csr_aliasing 6.970s 448.927us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.730s 133.567us 20 20 100.00
V2 TOTAL 1101 1101 100.00
V2S sec_cm_additional_check otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S tl_intg_err otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
otp_ctrl_tl_intg_err 36.290s 19.780ms 20 20 100.00
V2S prim_count_check otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S prim_fsm_check otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_bus_integrity otp_ctrl_tl_intg_err 36.290s 19.780ms 20 20 100.00
V2S sec_cm_secret_mem_scramble otp_ctrl_smoke 18.620s 6.853ms 50 50 100.00
V2S sec_cm_part_mem_digest otp_ctrl_smoke 18.620s 6.853ms 50 50 100.00
V2S sec_cm_dai_fsm_sparse otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_kdi_fsm_sparse otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_lci_fsm_sparse otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_part_fsm_sparse otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_scrmbl_fsm_sparse otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_timer_fsm_sparse otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_dai_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_kdi_seed_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_kdi_entropy_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_lci_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_part_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_scrmbl_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_timer_integ_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_timer_cnsty_ctr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_timer_lfsr_redun otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_dai_fsm_local_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_lci_fsm_local_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
V2S sec_cm_kdi_fsm_local_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
V2S sec_cm_part_fsm_local_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
otp_ctrl_macro_errs 1.178m 5.278ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_local_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
V2S sec_cm_timer_fsm_local_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_dai_fsm_global_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_lci_fsm_global_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
V2S sec_cm_kdi_fsm_global_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
V2S sec_cm_part_fsm_global_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
otp_ctrl_macro_errs 1.178m 5.278ms 50 50 100.00
V2S sec_cm_scrmbl_fsm_global_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
V2S sec_cm_timer_fsm_global_esc otp_ctrl_parallel_lc_esc 53.900s 15.589ms 200 200 100.00
otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_part_data_reg_integrity otp_ctrl_init_fail 8.720s 3.094ms 300 300 100.00
V2S sec_cm_part_data_reg_bkgn_chk otp_ctrl_check_fail 33.940s 5.533ms 50 50 100.00
V2S sec_cm_part_mem_regren otp_ctrl_dai_lock 54.150s 9.071ms 50 50 100.00
V2S sec_cm_part_mem_sw_unreadable otp_ctrl_dai_lock 54.150s 9.071ms 50 50 100.00
V2S sec_cm_part_mem_sw_unwritable otp_ctrl_dai_lock 54.150s 9.071ms 50 50 100.00
V2S sec_cm_lc_part_mem_sw_noaccess otp_ctrl_dai_lock 54.150s 9.071ms 50 50 100.00
V2S sec_cm_access_ctrl_mubi otp_ctrl_dai_lock 54.150s 9.071ms 50 50 100.00
V2S sec_cm_token_valid_ctrl_mubi otp_ctrl_smoke 18.620s 6.853ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi otp_ctrl_dai_lock 54.150s 9.071ms 50 50 100.00
V2S sec_cm_test_bus_lc_gated otp_ctrl_smoke 18.620s 6.853ms 50 50 100.00
V2S sec_cm_test_tl_lc_gate_fsm_sparse otp_ctrl_sec_cm 4.032m 42.561ms 5 5 100.00
V2S sec_cm_direct_access_config_regwen otp_ctrl_regwen 13.950s 5.237ms 50 50 100.00
V2S sec_cm_check_trigger_config_regwen otp_ctrl_smoke 18.620s 6.853ms 50 50 100.00
V2S sec_cm_check_config_regwen otp_ctrl_smoke 18.620s 6.853ms 50 50 100.00
V2S sec_cm_macro_mem_integrity otp_ctrl_macro_errs 1.178m 5.278ms 50 50 100.00
V2S TOTAL 25 25 100.00
V3 otp_ctrl_low_freq_read otp_ctrl_low_freq_read 20.920s 5.953ms 1 1 100.00
V3 stress_all_with_rand_reset otp_ctrl_stress_all_with_rand_reset 1.295h 1.884s 83 100 83.00
V3 TOTAL 84 101 83.17
TOTAL 1326 1343 98.73

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 17 17 17 100.00
V2S 2 2 2 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.93 93.89 96.30 95.48 92.12 97.05 96.33 93.35

Failure Buckets

Past Results