OTP_CTRL Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: `69c572b503`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.350s	778.541us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.840s	4.660ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.660s	1.539ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.030s	616.746us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	6.270s	136.238us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	10.200s	3.035ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.250s	1.705ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.030s	616.746us	20	20	100.00
		otp_ctrl_csr_aliasing	10.200s	3.035ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.930s	538.448us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.890s	569.564us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.720s	1.085ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.310s	2.140ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	36.220s	13.326ms	10	10	100.00
		otp_ctrl_check_fail	39.820s	21.377ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.680s	4.829ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.010m	19.105ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	59.220s	19.188ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	45.830s	13.939ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	50.670s	16.983ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.447m	8.339ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.143m	33.151ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	10.494m	90.057ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.070s	563.827us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.910s	837.002us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.000s	2.242ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.000s	2.242ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.660s	1.539ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	616.746us	20	20	100.00
		otp_ctrl_csr_aliasing	10.200s	3.035ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.890s	1.958ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.660s	1.539ms	5	5	100.00
		otp_ctrl_csr_rw	2.030s	616.746us	20	20	100.00
		otp_ctrl_csr_aliasing	10.200s	3.035ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.890s	1.958ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
		otp_ctrl_tl_intg_err	24.640s	4.486ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	24.640s	4.486ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.840s	4.660ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.840s	4.660ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
		otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
		otp_ctrl_macro_errs	1.447m	8.339ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
		otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
		otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
		otp_ctrl_macro_errs	1.447m	8.339ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.150s	14.759ms	200	200	100.00
		otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.310s	2.140ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	39.820s	21.377ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.010m	19.105ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.010m	19.105ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.010m	19.105ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.010m	19.105ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.010m	19.105ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.840s	4.660ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.010m	19.105ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.840s	4.660ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	6.480m	166.061ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.680s	4.829ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.840s	4.660ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.840s	4.660ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.447m	8.339ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.310s	6.901ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.167h	1.552s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.87	93.81	96.55	95.96	91.17	97.09	96.33	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.72235366278412928197337480244510181748955857941017970111188598404924188308726
    Line 575, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 578084933 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 578084933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.otp_ctrl_stress_all_with_rand_reset.49337764733513679022883451072586732967586639309739284391558422893410550187053
    Line 48432, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 199215151183 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 199215151183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 36.otp_ctrl_stress_all_with_rand_reset.18032517367650511661372112821575054407951344522943885335810025415556580055470
    Line 22317, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79936429466 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (580738348 [0x229d5d2c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 79936429466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.otp_ctrl_stress_all_with_rand_reset.59068985298855836460386617501500601866955879384210426471762390739292195035702
    Line 1098, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 914657407 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3638434192 [0xd8de1990] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 914657407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.102680636478387299054097305911385394418461934577106584680903223383719871701083
    Line 115798, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 343402197353 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 343402197353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 60.otp_ctrl_stress_all_with_rand_reset.74768866992525763811283864308392087521888989815095350524088389200226343907787
    Line 48869, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 447165978684 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 447165978684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

9.otp_ctrl_stress_all_with_rand_reset.36710668666352631085615057447913054820665111045167130239764126827774081994870
Line 67069, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 84226245099 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 84226568631 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 84226627455 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 84227392167 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 84227686287 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 35.otp_ctrl_stress_all_with_rand_reset.80797958896590330061622115963235935775236701486339767805832658156614323089557
    Line 62821, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47526055137 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 47526055137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:922) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 62.otp_ctrl_stress_all_with_rand_reset.62904051369163747335917712845312197308362071619405593473874421213887165569751
    Line 43347, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64631908911 ps: (otp_ctrl_scoreboard.sv:922) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (264220 [0x4081c] vs 264216 [0x40818]) reg name: status, compare_mask 40800
  UVM_INFO @ 64631908911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```