OTP_CTRL Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.730s	52.688us	1	1	100.00
V1	smoke	otp_ctrl_smoke	28.110s	2.748ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.020s	1.574ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.080s	164.198us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.560s	6.892ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.990s	2.466ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.390s	1.712ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.080s	164.198us	20	20	100.00
		otp_ctrl_csr_aliasing	6.990s	2.466ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.040s	564.512us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.170s	503.219us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.630s	1.021ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.760s	1.933ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	50.190s	19.575ms	10	10	100.00
		otp_ctrl_check_fail	1.703m	9.151ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.020s	4.693ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	50.510s	7.977ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	46.620s	1.795ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.220s	10.190ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	46.790s	2.603ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.510m	31.948ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.173m	11.894ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	9.702m	56.724ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.530s	591.990us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.720s	1.041ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.940s	3.136ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.940s	3.136ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.020s	1.574ms	5	5	100.00
		otp_ctrl_csr_rw	2.080s	164.198us	20	20	100.00
		otp_ctrl_csr_aliasing	6.990s	2.466ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.050s	508.087us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.020s	1.574ms	5	5	100.00
		otp_ctrl_csr_rw	2.080s	164.198us	20	20	100.00
		otp_ctrl_csr_aliasing	6.990s	2.466ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.050s	508.087us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
		otp_ctrl_tl_intg_err	24.750s	10.298ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	24.750s	10.298ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	28.110s	2.748ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	28.110s	2.748ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
		otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
		otp_ctrl_macro_errs	1.510m	31.948ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
		otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
		otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
		otp_ctrl_macro_errs	1.510m	31.948ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	35.720s	11.273ms	200	200	100.00
		otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.760s	1.933ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.703m	9.151ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	50.510s	7.977ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	50.510s	7.977ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	50.510s	7.977ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	50.510s	7.977ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	50.510s	7.977ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	28.110s	2.748ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	50.510s	7.977ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	28.110s	2.748ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.994m	43.949ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.020s	4.693ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	28.110s	2.748ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	28.110s	2.748ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.510m	31.948ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.820s	7.606ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.179h	1.976s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.85	93.84	96.23	95.31	92.12	96.76	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.112634275320134054922377716654427270998007921677540214609392277635224949667830
    Line 2886, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1034300309 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 1034300309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.otp_ctrl_stress_all_with_rand_reset.50087311878502018545370056578608600448272988971083090105285493341570042099303
    Line 40949, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20423862300 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 20423862300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 20.otp_ctrl_stress_all_with_rand_reset.68005616892111253658130379294624051680247039629286815760311129426753523613594
    Line 388, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 301275510 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (98277609 [0x5db98e9] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 301275510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.otp_ctrl_stress_all_with_rand_reset.20748820709230732210614627801573887742312377597941526200292380142822615926091
    Line 15066, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7795042221 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4262732015 [0xfe1420ef] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 7795042221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.109968843441447893497653745114283595119677550120533705746199523679547706480361
    Line 2816, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9426067708 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 9426067708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

14.otp_ctrl_stress_all_with_rand_reset.36760345081338550896012180106549174495407651831615473609030224615227969838212
Line 10235, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 104635076223 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 104639742899 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 104639909566 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 104643076239 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 104643242906 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 81.otp_ctrl_stress_all_with_rand_reset.2908372277805495318145433566687912210464649051867947076091560505406482119389
    Line 8561, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9999874933 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 9999874933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```