OTP_CTRL Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: `349bab6601`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.770s	104.232us	1	1	100.00
V1	smoke	otp_ctrl_smoke	16.010s	2.037ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.850s	1.441ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.940s	571.425us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	18.960s	8.065ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.590s	3.030ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.380s	114.685us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.940s	571.425us	20	20	100.00
		otp_ctrl_csr_aliasing	7.590s	3.030ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.810s	510.589us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.980s	537.465us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.680s	5.090ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.250s	2.817ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	33.890s	1.519ms	10	10	100.00
		otp_ctrl_check_fail	57.100s	26.468ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.880s	4.301ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	50.510s	17.526ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.627m	8.271ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	45.020s	14.499ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	45.110s	12.731ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	4.143m	32.005ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	53.590s	22.007ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.686m	52.836ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.180s	564.332us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.280s	214.516us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	9.360s	2.632ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	9.360s	2.632ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.850s	1.441ms	5	5	100.00
		otp_ctrl_csr_rw	1.940s	571.425us	20	20	100.00
		otp_ctrl_csr_aliasing	7.590s	3.030ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.110s	1.175ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.850s	1.441ms	5	5	100.00
		otp_ctrl_csr_rw	1.940s	571.425us	20	20	100.00
		otp_ctrl_csr_aliasing	7.590s	3.030ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.110s	1.175ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
		otp_ctrl_tl_intg_err	42.740s	18.854ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	42.740s	18.854ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	16.010s	2.037ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	16.010s	2.037ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
		otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
		otp_ctrl_macro_errs	4.143m	32.005ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
		otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
		otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
		otp_ctrl_macro_errs	4.143m	32.005ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	32.940s	10.960ms	200	200	100.00
		otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.250s	2.817ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	57.100s	26.468ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	50.510s	17.526ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	50.510s	17.526ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	50.510s	17.526ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	50.510s	17.526ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	50.510s	17.526ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	16.010s	2.037ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	50.510s	17.526ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	16.010s	2.037ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.097m	155.062ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.880s	4.301ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	16.010s	2.037ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	16.010s	2.037ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	4.143m	32.005ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.180s	6.923ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.208h	2.692s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.85	93.83	96.32	95.56	91.65	97.00	96.33	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.75066699918380453686151401963507707154245458957283140234713177179207195968677
    Line 25125, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 262885709451 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 262885709451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.otp_ctrl_stress_all_with_rand_reset.85543503966484502714064778205626606428944031878423477016309645472299805988314
    Line 47954, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171600648962 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 171600648962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 5 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 5 failures.
  - 37.otp_ctrl_stress_all_with_rand_reset.5357778018208189595606563935240395238965522111737132230836167610810096733291
    Line 41764, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 382218135067 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2025147521 [0x78b54c81]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_1
  UVM_INFO @ 382218135067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.otp_ctrl_stress_all_with_rand_reset.81338741440382040422449730901813044857416958332504077145058943908706345359052
    Line 74318, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120459078221 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (241252150 [0xe613736] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 120459078221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed

has 3 failures:

Test otp_ctrl_stress_all_with_rand_reset has 3 failures.

6.otp_ctrl_stress_all_with_rand_reset.73730626610674348013072858234869945882575075634600155123049841485140631809895
Line 7086, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 19515242345 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 19516220113 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 19516286779 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 19517086771 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 19517086771 ps: (dv_base_reg.sv:325) [otp_ctrl_core_reg_block.direct_access_regwen] lock_lockable_flds          0 val

14.otp_ctrl_stress_all_with_rand_reset.23745675074995910629830502940508723347983420272671106202641949734660318680526
Line 4723, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 22416132503 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 22416732503 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22416772503 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22418172503 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 22418212503 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

... and 1 more failures.

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *dc rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 51.otp_ctrl_stress_all_with_rand_reset.108378927991260785241217869041615317609485522712535640776892058377359574566922
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15833408379 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3409840859 [0xcb3e0adb]) dai addr 6dc rdata0 readout mismatch
  UVM_INFO @ 15833408379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```