OTP_CTRL Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.640s	55.608us	1	1	100.00
V1	smoke	otp_ctrl_smoke	14.930s	4.589ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.400s	288.778us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.380s	581.699us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.160s	1.356ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.870s	2.549ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.160s	1.577ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.380s	581.699us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	2.549ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.650s	545.109us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.650s	563.957us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.510s	1.281ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.120s	3.014ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	49.040s	7.196ms	10	10	100.00
		otp_ctrl_check_fail	54.710s	27.373ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.750s	398.418us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.367m	6.295ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	41.030s	1.413ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	32.400s	11.758ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	49.330s	17.142ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.500m	9.231ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	54.960s	6.566ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.180m	164.117ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.140s	599.469us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.640s	746.553us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	11.320s	2.886ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	11.320s	2.886ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.400s	288.778us	5	5	100.00
		otp_ctrl_csr_rw	2.380s	581.699us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	2.549ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.760s	1.535ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.400s	288.778us	5	5	100.00
		otp_ctrl_csr_rw	2.380s	581.699us	20	20	100.00
		otp_ctrl_csr_aliasing	5.870s	2.549ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.760s	1.535ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.500s	18.934ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.500s	18.934ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	14.930s	4.589ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	14.930s	4.589ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
		otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
		otp_ctrl_macro_errs	1.500m	9.231ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
		otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
		otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
		otp_ctrl_macro_errs	1.500m	9.231ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.240s	13.583ms	200	200	100.00
		otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.120s	3.014ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	54.710s	27.373ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.367m	6.295ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.367m	6.295ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.367m	6.295ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.367m	6.295ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.367m	6.295ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	14.930s	4.589ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.367m	6.295ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	14.930s	4.589ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.357m	40.929ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.750s	398.418us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	14.930s	4.589ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	14.930s	4.589ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.500m	9.231ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	11.310s	3.038ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.089h	2.501s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.03	93.88	96.75	96.07	91.65	97.19	96.33	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 3.otp_ctrl_stress_all_with_rand_reset.79638896492311581500741441676333538781596306608296932104765969893107564864001
      Line 84184, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 77568236747 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2167826010 [0x8136665a] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 77568236747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 26.otp_ctrl_stress_all_with_rand_reset.16544091172517930278210302450848212738592107736663356858069614475864645689190
      Line 330, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  70947572 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3567823997 [0xd4a8ac7d] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @  70947572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 4.otp_ctrl_stress_all_with_rand_reset.59873886900253243818696572112187075452992667511105936736845538070659806216186
      Line 8978, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 156184526125 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 156184526125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.otp_ctrl_stress_all_with_rand_reset.53944255023715939867902357478017343912601933826176109154948880335282832665794
      Line 34352, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15638785541 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 15638785541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.62671074780665903502533664409483644719286618373094883996346575266422866909334
      Line 29505, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36482801543 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 36482801543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_stress_all_with_rand_reset.29413998309869173997542096140493770599490722090337126839529596741444817274926
      Line 356, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 214394857 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 214394857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 11.otp_ctrl_stress_all_with_rand_reset.44867691947663379888551093609452548991004281489592912365173346149308083142888
      Line 274, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14076887225 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2643713487 [0x9d93ddcf]) dai addr 72c rdata0 readout mismatch
        UVM_INFO @ 14076887225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 31.otp_ctrl_stress_all_with_rand_reset.67324199357152000966057377095377049836485511378467959151575818478990780957803
      Line 50772, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 238830045279 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 796 [0x31c]) dai addr 31c rdata0 readout mismatch
        UVM_INFO @ 238830045279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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