OTP_CTRL Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	58.102us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.810s	6.983ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.460s	204.699us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.620s	661.901us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.120s	619.868us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.790s	208.294us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.140s	445.267us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.620s	661.901us	20	20	100.00
		otp_ctrl_csr_aliasing	6.790s	208.294us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.500s	135.583us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.730s	513.955us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	19.760s	1.017ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.790s	2.622ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	35.860s	12.522ms	10	10	100.00
		otp_ctrl_check_fail	1.158m	18.746ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.310s	4.636ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	56.080s	30.884ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	51.500s	4.667ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	30.140s	10.674ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.740s	25.303ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.083m	26.904ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	50.190s	19.166ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.812m	54.913ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.990s	549.307us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.110s	921.614us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.280s	750.388us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.280s	750.388us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.460s	204.699us	5	5	100.00
		otp_ctrl_csr_rw	2.620s	661.901us	20	20	100.00
		otp_ctrl_csr_aliasing	6.790s	208.294us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.490s	136.021us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.460s	204.699us	5	5	100.00
		otp_ctrl_csr_rw	2.620s	661.901us	20	20	100.00
		otp_ctrl_csr_aliasing	6.790s	208.294us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.490s	136.021us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
		otp_ctrl_tl_intg_err	34.440s	19.806ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	34.440s	19.806ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.810s	6.983ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.810s	6.983ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
		otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
		otp_ctrl_macro_errs	1.083m	26.904ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
		otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
		otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
		otp_ctrl_macro_errs	1.083m	26.904ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.970s	17.820ms	200	200	100.00
		otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.790s	2.622ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.158m	18.746ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	56.080s	30.884ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	56.080s	30.884ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	56.080s	30.884ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	56.080s	30.884ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	56.080s	30.884ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.810s	6.983ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	56.080s	30.884ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.810s	6.983ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.986m	17.800ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.310s	4.636ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.810s	6.983ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.810s	6.983ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.083m	26.904ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.110s	3.112ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.490h	228.839ms	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1325	1343	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.85	93.83	96.15	95.71	91.65	97.00	96.33	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.55808817679037010073172172929757948875152862485242700075726258654425996902293
    Line 330, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 536622057 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2750826577 [0xa3f64851] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 536622057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.otp_ctrl_stress_all_with_rand_reset.42031040772075288303154998593676903427214136269918505857099929975119481526526
    Line 27390, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10225456401 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4247530902 [0xfd2c2d96] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 10225456401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 31.otp_ctrl_stress_all_with_rand_reset.30863987680620072630143891306004653311719790937321308805656217967659638538081
    Line 26327, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 96618310690 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 96618310690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.otp_ctrl_stress_all_with_rand_reset.75805228520517445911365284161238058831533738570381739982361559645015263332429
    Line 8905, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17134091971 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 17134091971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 29.otp_ctrl_stress_all_with_rand_reset.6234553655529400130258995865454889277500795529131714897571360109345912451451
    Line 269, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  30368570 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  30368570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 79.otp_ctrl_stress_all_with_rand_reset.40025394131930331863553817481738789425325276712384247788304867598072659130716
    Line 40284, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 7593858155 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 7593858155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

84.otp_ctrl_stress_all_with_rand_reset.35224738743971417800414328847346417068605231969742959982525332450100009313027
Line 114324, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 499785768703 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 499788768709 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 499790268712 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 499794768721 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 499795435389 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 89.otp_ctrl_stress_all_with_rand_reset.40594147928039635498203967511012137113798473836461110508827417020454833908543
    Line 15671, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33106601255 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
  UVM_INFO @ 33106601255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```