OTP_CTRL Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.840s	56.868us	1	1	100.00
V1	smoke	otp_ctrl_smoke	22.990s	8.003ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.590s	374.532us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.470s	622.415us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.280s	1.523ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.530s	1.235ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.940s	1.791ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.470s	622.415us	20	20	100.00
		otp_ctrl_csr_aliasing	6.530s	1.235ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.550s	135.416us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.760s	556.751us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	26.100s	9.946ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	9.700s	2.874ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	25.100s	1.036ms	10	10	100.00
		otp_ctrl_check_fail	55.100s	14.569ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.330s	630.918us	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.426m	7.027ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	56.430s	19.364ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	39.840s	11.953ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	50.240s	18.472ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.445m	29.538ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.162m	7.633ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	12.298m	76.474ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.160s	561.011us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.630s	583.674us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.000s	369.189us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.000s	369.189us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.590s	374.532us	5	5	100.00
		otp_ctrl_csr_rw	2.470s	622.415us	20	20	100.00
		otp_ctrl_csr_aliasing	6.530s	1.235ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.430s	1.503ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.590s	374.532us	5	5	100.00
		otp_ctrl_csr_rw	2.470s	622.415us	20	20	100.00
		otp_ctrl_csr_aliasing	6.530s	1.235ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.430s	1.503ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
		otp_ctrl_tl_intg_err	26.530s	20.006ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	26.530s	20.006ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	22.990s	8.003ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	22.990s	8.003ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
		otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
		otp_ctrl_macro_errs	1.445m	29.538ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
		otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
		otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
		otp_ctrl_macro_errs	1.445m	29.538ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	45.120s	16.735ms	200	200	100.00
		otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	9.700s	2.874ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	55.100s	14.569ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.426m	7.027ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.426m	7.027ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.426m	7.027ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.426m	7.027ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.426m	7.027ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	22.990s	8.003ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.426m	7.027ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	22.990s	8.003ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.926m	154.626ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.330s	630.918us	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	22.990s	8.003ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	22.990s	8.003ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.445m	29.538ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.550s	3.061ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.407h	1.752s	81	100	81.00
V3		TOTAL			82	101	81.19
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.91	93.89	96.23	95.57	91.89	97.09	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.60878806249605733802595516470573358124338487637771655888934561133777133338018
    Line 332, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  30282077 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1314325352 [0x4e570368] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  30282077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.otp_ctrl_stress_all_with_rand_reset.16682524910336940744585152633713986155221487288723339912072765626562478613795
    Line 37941, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 61108076137 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2385269931 [0x8e2c54ab] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 61108076137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 20.otp_ctrl_stress_all_with_rand_reset.52382392666656883655300372345192814240297683907028639718346197891981649926162
    Line 1173, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127304654 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 127304654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.otp_ctrl_stress_all_with_rand_reset.101830905797399291814587471517481741186854969152674859393312242440438711543157
    Line 14253, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17809849605 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 17809849605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 23.otp_ctrl_stress_all_with_rand_reset.63034907595469250246004479938489286231258364465818957171043961101037827514145
    Line 9994, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 2453559906 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 2453559906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *e* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 58.otp_ctrl_stress_all_with_rand_reset.105518586907420524807731722801904917862748794937104929687789087479598673931476
    Line 15749, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20589421754 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1256 [0x4e8]) dai addr 4e8 rdata0 readout mismatch
  UVM_INFO @ 20589421754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

61.otp_ctrl_stress_all_with_rand_reset.99419000176016270277108992158429328075837631687193703808053363330062477637717
Line 33513, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 158594564593 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 158597064598 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 158598564601 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 158605231281 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 158606731284 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 73.otp_ctrl_stress_all_with_rand_reset.3230308116066709415783987992402715657102989330705730231841852672946306247261
    Line 2689, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27562597361 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1602815804 [0x5f89073c]) dai addr 744 rdata0 readout mismatch
  UVM_INFO @ 27562597361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```