OTP_CTRL Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.750s	50.305us	1	1	100.00
V1	smoke	otp_ctrl_smoke	13.460s	2.214ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.350s	200.423us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.640s	692.441us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.840s	497.389us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.080s	316.863us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.060s	103.168us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.640s	692.441us	20	20	100.00
		otp_ctrl_csr_aliasing	6.080s	316.863us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.520s	130.080us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.480s	95.056us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.290s	616.987us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.800s	2.561ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	40.090s	13.784ms	10	10	100.00
		otp_ctrl_check_fail	53.910s	20.752ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	14.940s	4.659ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	55.510s	24.962ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	42.350s	2.458ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	37.050s	13.245ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	55.600s	15.368ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.097m	18.832ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	52.920s	39.098ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.644m	64.158ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.260s	566.070us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.600s	434.285us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.420s	793.186us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.420s	793.186us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.350s	200.423us	5	5	100.00
		otp_ctrl_csr_rw	2.640s	692.441us	20	20	100.00
		otp_ctrl_csr_aliasing	6.080s	316.863us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.510s	494.184us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.350s	200.423us	5	5	100.00
		otp_ctrl_csr_rw	2.640s	692.441us	20	20	100.00
		otp_ctrl_csr_aliasing	6.080s	316.863us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.510s	494.184us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
		otp_ctrl_tl_intg_err	29.800s	19.033ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	29.800s	19.033ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	13.460s	2.214ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	13.460s	2.214ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
		otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
		otp_ctrl_macro_errs	1.097m	18.832ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
		otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
		otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
		otp_ctrl_macro_errs	1.097m	18.832ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	37.340s	13.589ms	200	200	100.00
		otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.800s	2.561ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	53.910s	20.752ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	55.510s	24.962ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	55.510s	24.962ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	55.510s	24.962ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	55.510s	24.962ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	55.510s	24.962ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	13.460s	2.214ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	55.510s	24.962ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	13.460s	2.214ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	7.641m	165.158ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	14.940s	4.659ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	13.460s	2.214ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	13.460s	2.214ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.097m	18.832ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	18.530s	7.532ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.038h	1.311s	78	100	78.00
V3		TOTAL			79	101	78.22
		TOTAL			1321	1343	98.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.06	93.89	96.77	96.17	91.65	97.24	96.33	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 11 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 11 failures.

    • 11.otp_ctrl_stress_all_with_rand_reset.71334553738723902751597186040397759566515075681162672245373336229230378287767
      Line 49029, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 261884507858 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 261884507858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 13.otp_ctrl_stress_all_with_rand_reset.10195904075336692046226391874453948327937615431770193558772109312567051967151
      Line 3614, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1490175958 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 1490175958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 6 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 6 failures.

    • 9.otp_ctrl_stress_all_with_rand_reset.1490246645082430112150025897053838152283133329908226313023497052763936447505
      Line 20109, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35493593453 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3059870611 [0xb661eb93] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 35493593453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.otp_ctrl_stress_all_with_rand_reset.76408368487761296079936772763839076833294782316007606718295726569112174536329
      Line 9520, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 522896340766 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1884536123 [0x7053bd3b] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 522896340766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• Offending '(cio_test_en_o == *)' has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 30.otp_ctrl_stress_all_with_rand_reset.108744677303997515941862627664791519881815298932968229745511520637193888913173
      Line 1945, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 18970904660 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 18970904660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 65.otp_ctrl_stress_all_with_rand_reset.96356327983976672782775463782898129469704652536438161381783019642951519517376
      Line 99161, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 31204033163 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 31204033163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 25.otp_ctrl_stress_all_with_rand_reset.85085756188436231870205448180195104519788113806121120967499404838730008401894
      Line 272, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8355821106 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1420 [0x58c]) dai addr 58c rdata0 readout mismatch
        UVM_INFO @ 8355821106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 55.otp_ctrl_stress_all_with_rand_reset.39345438778286609426912212922242090083732248860083369883474629025776660402531
      Line 1404, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2371762595 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 2371762595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 94.otp_ctrl_stress_all_with_rand_reset.73490630226993405375039804633589801160337916426468101870980086145380097147805
      Line 26529, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3447430069 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.err_code_11
        UVM_INFO @ 3447430069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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