OTP_CTRL Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.750s	201.852us	1	1	100.00
V1	smoke	otp_ctrl_smoke	20.280s	8.359ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.580s	394.673us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.850s	84.807us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.170s	6.350ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.990s	453.752us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.980s	1.679ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.850s	84.807us	20	20	100.00
		otp_ctrl_csr_aliasing	5.990s	453.752us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.620s	518.441us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.400s	39.252us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.280s	9.923ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	10.640s	2.987ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	42.260s	3.989ms	10	10	100.00
		otp_ctrl_check_fail	1.088m	28.435ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	17.210s	4.916ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	45.460s	4.116ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	40.410s	2.735ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	29.520s	11.469ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.015m	24.225ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.070m	15.748ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.648m	12.215ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.556m	122.427ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.300s	569.126us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.310s	778.024us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.750s	3.122ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.750s	3.122ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.580s	394.673us	5	5	100.00
		otp_ctrl_csr_rw	1.850s	84.807us	20	20	100.00
		otp_ctrl_csr_aliasing	5.990s	453.752us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.140s	2.158ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.580s	394.673us	5	5	100.00
		otp_ctrl_csr_rw	1.850s	84.807us	20	20	100.00
		otp_ctrl_csr_aliasing	5.990s	453.752us	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.140s	2.158ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
		otp_ctrl_tl_intg_err	35.360s	18.959ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	35.360s	18.959ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	20.280s	8.359ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	20.280s	8.359ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
		otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
		otp_ctrl_macro_errs	2.070m	15.748ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
		otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
		otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
		otp_ctrl_macro_errs	2.070m	15.748ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	34.180s	15.516ms	200	200	100.00
		otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	10.640s	2.987ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.088m	28.435ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	45.460s	4.116ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	45.460s	4.116ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	45.460s	4.116ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	45.460s	4.116ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	45.460s	4.116ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	20.280s	8.359ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	45.460s	4.116ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	20.280s	8.359ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.636m	40.297ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	17.210s	4.916ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	20.280s	8.359ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	20.280s	8.359ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.070m	15.748ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.570s	5.949ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.372h	1.256s	82	100	82.00
V3		TOTAL			83	101	82.18
		TOTAL			1324	1343	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.93	93.95	96.30	95.79	91.65	97.15	96.33	93.35

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 10 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 10 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.770129512141714769311321810614664710184879673776484365574450529016175919609
    Line 346, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 602555701 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 602555701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.otp_ctrl_stress_all_with_rand_reset.35664183934199471640947195847937561854432079115600144976379366110580215195866
    Line 14732, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7261212213 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 7261212213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 6.otp_ctrl_csr_mem_rw_with_rand_reset.8981055249860588023563449655972945802578237551438272500496074878835661563237
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 931822819 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 931822819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 31.otp_ctrl_stress_all_with_rand_reset.113488368737717181102448081371906081023910108199841311438778349646786001321880
    Line 1296, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 19776330149 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 19776330149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 49.otp_ctrl_stress_all_with_rand_reset.85561728481474254069570206492947020302217989209391892163447778675994356827138
    Line 31162, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 269722164005 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 269722164005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 12.otp_ctrl_stress_all_with_rand_reset.20548894881251842754787464905433994716174323683161149616273675071630629813257
    Line 6335, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 727351537336 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (674192899 [0x282f5e03] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 727351537336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 66.otp_ctrl_stress_all_with_rand_reset.71990897542637809316943221138234931262638865895435990153401868160668519736557
    Line 1580, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 422382379 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2667036727 [0x9ef7c037] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 422382379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 55.otp_ctrl_stress_all_with_rand_reset.102468718868609655320437040305481158050321955385272035247601029598508062500727
    Line 10051, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131857881076 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 131857881076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 74.otp_ctrl_stress_all_with_rand_reset.85786056480794027833777537815078508247407666586448448699314013668830418178246
    Line 4029, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 43975077729 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 812 [0x32c]) dai addr 32c rdata0 readout mismatch
  UVM_INFO @ 43975077729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 97.otp_ctrl_stress_all_with_rand_reset.21053526354621770990102901133447048519314747401186157370975309194767152889962
    Line 12305, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17909523730 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1488 [0x5d0]) dai addr 5d0 rdata0 readout mismatch
  UVM_INFO @ 17909523730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

OTP_CTRL Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0e5093d709`