OTP_CTRL Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: `8cb25a6867`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	84.626us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.290s	4.460ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.450s	179.561us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.360s	635.829us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.810s	419.338us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	7.830s	2.519ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.140s	1.611ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.360s	635.829us	20	20	100.00
		otp_ctrl_csr_aliasing	7.830s	2.519ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.850s	554.153us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.690s	525.352us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.670s	780.253us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.980s	2.665ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	40.380s	8.837ms	10	10	100.00
		otp_ctrl_check_fail	40.200s	18.534ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	12.860s	4.264ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	50.010s	8.241ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	43.760s	25.033ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	29.350s	1.959ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.277m	25.677ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	49.130s	4.399ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.141m	23.574ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.039m	70.494ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.250s	560.802us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	3.050s	433.126us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.020s	2.960ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.020s	2.960ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.450s	179.561us	5	5	100.00
		otp_ctrl_csr_rw	2.360s	635.829us	20	20	100.00
		otp_ctrl_csr_aliasing	7.830s	2.519ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.800s	272.497us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.450s	179.561us	5	5	100.00
		otp_ctrl_csr_rw	2.360s	635.829us	20	20	100.00
		otp_ctrl_csr_aliasing	7.830s	2.519ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.800s	272.497us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
		otp_ctrl_tl_intg_err	38.930s	20.170ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	38.930s	20.170ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.290s	4.460ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.290s	4.460ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
		otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
		otp_ctrl_macro_errs	49.130s	4.399ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
		otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
		otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
		otp_ctrl_macro_errs	49.130s	4.399ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	36.420s	13.289ms	200	200	100.00
		otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.980s	2.665ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	40.200s	18.534ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	50.010s	8.241ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	50.010s	8.241ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	50.010s	8.241ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	50.010s	8.241ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	50.010s	8.241ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.290s	4.460ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	50.010s	8.241ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.290s	4.460ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.771m	172.964ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	12.860s	4.264ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.290s	4.460ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.290s	4.460ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	49.130s	4.399ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	13.870s	5.972ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.229h	461.297ms	80	100	80.00
V3		TOTAL			81	101	80.20
		TOTAL			1322	1343	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.88	93.84	96.17	95.86	91.65	97.05	96.33	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 3.otp_ctrl_stress_all_with_rand_reset.18723037688413314235023641677610119761705523170841686166141387164610073601063
    Line 17533, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 95794729299 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1122025400 [0x42e0bfb8] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 95794729299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.otp_ctrl_stress_all_with_rand_reset.13609816344195056380100719680268378934633967508141938742685584607582357974506
    Line 17582, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 15413441845 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (950494519 [0x38a76537] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 15413441845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1129) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 6 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 6 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.49680944486039056100579703080330576383296768960991133673990713116287185093884
    Line 95562, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 209931624794 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 209931624794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.otp_ctrl_stress_all_with_rand_reset.20959997193163047066896217654835278916800206473031144237909907194554734031359
    Line 30901, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 141614698540 ps: (otp_ctrl_scoreboard.sv:1129) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 141614698540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.otp_ctrl_csr_mem_rw_with_rand_reset.81579386252479548098926362148195307146987328747697958722022138064215748554138
    Line 276, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  58573882 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  58573882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.96941127939232166959388754937033886313345069949692199752806729593967635656317
    Line 60873, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1068430079055 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1068430079055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 79.otp_ctrl_stress_all_with_rand_reset.3547980525933460497251607225387777291917086462660738917751805035070907205629
    Line 13546, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1448883117 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1448883117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

54.otp_ctrl_stress_all_with_rand_reset.54916121746855576747899367272420819834954454315491397638383542732466606754739
Line 21611, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 42429687428 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 42429973140 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 42430034364 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 42430748644 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 42430871092 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

77.otp_ctrl_stress_all_with_rand_reset.74003960645278655255104651442645783909157448878047957343962578596870075171180
Line 5535, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 2433184793 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 2433413956 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2433476455 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2433851449 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 2433997280 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *a* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 16.otp_ctrl_stress_all_with_rand_reset.33112833076276156396331360280109389796531356511981360068984182273392207859172
    Line 333, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14020498633 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1696 [0x6a0]) dai addr 6a0 rdata0 readout mismatch
  UVM_INFO @ 14020498633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *d* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 58.otp_ctrl_stress_all_with_rand_reset.26372818824338075759635800383042896483625506082412004454648277828423322641278
    Line 1549, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 53317345416 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 468 [0x1d4]) dai addr 1d4 rdata0 readout mismatch
  UVM_INFO @ 53317345416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```