OTP_CTRL Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	106.360us	1	1	100.00
V1	smoke	otp_ctrl_smoke	25.470s	9.696ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.770s	379.846us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.140s	596.693us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	7.440s	1.987ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.590s	190.763us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.760s	1.659ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.140s	596.693us	20	20	100.00
		otp_ctrl_csr_aliasing	6.590s	190.763us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.770s	530.177us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.520s	37.481us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	20.220s	609.913us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.920s	2.303ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	44.680s	25.287ms	10	10	100.00
		otp_ctrl_check_fail	49.080s	25.349ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.000s	4.741ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	57.920s	4.163ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	55.260s	25.296ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	28.100s	9.405ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	53.800s	6.385ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.675m	18.931ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.202m	24.204ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.077m	218.974ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.180s	593.933us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.930s	1.035ms	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.700s	2.193ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.700s	2.193ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.770s	379.846us	5	5	100.00
		otp_ctrl_csr_rw	2.140s	596.693us	20	20	100.00
		otp_ctrl_csr_aliasing	6.590s	190.763us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.710s	251.373us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.770s	379.846us	5	5	100.00
		otp_ctrl_csr_rw	2.140s	596.693us	20	20	100.00
		otp_ctrl_csr_aliasing	6.590s	190.763us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.710s	251.373us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
		otp_ctrl_tl_intg_err	23.980s	5.067ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	23.980s	5.067ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	25.470s	9.696ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	25.470s	9.696ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
		otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
		otp_ctrl_macro_errs	1.675m	18.931ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
		otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
		otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
		otp_ctrl_macro_errs	1.675m	18.931ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	52.830s	17.990ms	200	200	100.00
		otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.920s	2.303ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	49.080s	25.349ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	57.920s	4.163ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	57.920s	4.163ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	57.920s	4.163ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	57.920s	4.163ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	57.920s	4.163ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	25.470s	9.696ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	57.920s	4.163ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	25.470s	9.696ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.748m	154.685ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.000s	4.741ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	25.470s	9.696ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	25.470s	9.696ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.675m	18.931ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.160s	3.049ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.308h	2.104s	84	100	84.00
V3		TOTAL			85	101	84.16
		TOTAL			1327	1343	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.94	93.89	96.27	95.48	92.12	97.10	96.33	93.35

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 8 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.8299103770856227379720621338310010960874253561082252894527073569069923131835
      Line 15156, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 88444438438 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 88444438438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.otp_ctrl_stress_all_with_rand_reset.4274132678651616191634661729624601378312156771444180337586360548734460135996
      Line 21614, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 169874886646 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 169874886646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 7 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 7 failures.

    • 6.otp_ctrl_stress_all_with_rand_reset.10581049453642316692291293444499245492945336486518713549046128173669915571282
      Line 1344, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3750447351 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4250968185 [0xfd60a079] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 3750447351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 41.otp_ctrl_stress_all_with_rand_reset.21511636824328483580715232145284942359777919755445545008811171499109286338367
      Line 32706, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10750839081 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1861411486 [0x6ef2e29e] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 10750839081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Offending '(cio_test_en_o == *)' has 1 failures:
  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 59.otp_ctrl_stress_all_with_rand_reset.11157600258807214265536718886572007582048364192696602590920609435731870027655
      Line 27704, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @ 17645738859 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @ 17645738859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.05.31_04.49.10
• 2024.05.29_03.17.55
• 2024.05.27_04.25.28
• 2024.05.24_04.30.17
• 2024.05.22_04.28.16
• 2024.05.20_04.01.08