OTP_CTRL Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: `a182fcef27`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.830s	102.162us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.010s	8.438ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.940s	1.555ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.040s	667.946us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	11.910s	1.006ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	10.440s	2.557ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.390s	1.578ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.040s	667.946us	20	20	100.00
		otp_ctrl_csr_aliasing	10.440s	2.557ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.520s	552.523us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.500s	137.401us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	18.230s	640.682us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.320s	2.696ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	36.130s	6.012ms	10	10	100.00
		otp_ctrl_check_fail	57.780s	28.223ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	13.110s	4.174ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.193m	32.389ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	52.710s	2.528ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	35.590s	12.864ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	59.530s	16.820ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.153m	25.571ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	50.130s	31.525ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	7.720m	40.763ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.110s	535.592us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	4.100s	353.103us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.340s	697.910us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.340s	697.910us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.940s	1.555ms	5	5	100.00
		otp_ctrl_csr_rw	2.040s	667.946us	20	20	100.00
		otp_ctrl_csr_aliasing	10.440s	2.557ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.050s	1.443ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.940s	1.555ms	5	5	100.00
		otp_ctrl_csr_rw	2.040s	667.946us	20	20	100.00
		otp_ctrl_csr_aliasing	10.440s	2.557ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.050s	1.443ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
		otp_ctrl_tl_intg_err	29.740s	2.553ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	29.740s	2.553ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.010s	8.438ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.010s	8.438ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
		otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
		otp_ctrl_macro_errs	1.153m	25.571ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
		otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
		otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
		otp_ctrl_macro_errs	1.153m	25.571ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	39.310s	11.705ms	200	200	100.00
		otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.320s	2.696ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	57.780s	28.223ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.193m	32.389ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.193m	32.389ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.193m	32.389ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.193m	32.389ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.193m	32.389ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.010s	8.438ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.193m	32.389ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.010s	8.438ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.700m	21.573ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	13.110s	4.174ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.010s	8.438ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.010s	8.438ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.153m	25.571ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.490s	3.078ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.257h	1.921s	90	100	90.00
V3		TOTAL			91	101	90.10
		TOTAL			1333	1343	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.81	93.84	96.17	95.48	91.65	97.00	96.26	93.28

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.46368319842496432634685787625184328791699379690617408277247427413016902616834
    Line 66019, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 541213144064 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 541213144064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.otp_ctrl_stress_all_with_rand_reset.111251997327719971177079195770528575695449400519521709655597653122437897623255
    Line 45608, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20386252519 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 20386252519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Offending '(cio_test_en_o == *)' has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 1.otp_ctrl_stress_all_with_rand_reset.71556427457142228155741225401698990511040165883837478251429272314522548839525
    Line 41986, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 27503377228 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 27503377228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.16850714397247620001871424813400389276345817273550172038254743221994285848759
    Line 467, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1579497346 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1579497346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 17.otp_ctrl_stress_all_with_rand_reset.8505527396028201693097031395830077305772844940596530813146209848031894969249
    Line 72224, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 287746040936 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1120896422 [0x42cf85a6] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 287746040936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.otp_ctrl_stress_all_with_rand_reset.103440054258457455874079107749434444567990761860422641072625436032919705656547
    Line 302, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  28238722 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (118508855 [0x7104d37] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @  28238722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

63.otp_ctrl_stress_all_with_rand_reset.1423579922327340665636844800491210497202137265036732098176594391546076743433
Line 15181, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 28988506292 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 28988787542 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 28989131292 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 28989787542 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 28989975042 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1