OTP_CTRL Simulation Results

Wednesday June 05 2024 22:14:46 UTC

GitHub Revision: `b29ffbb03c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 104714960319679935410420483500971829136303708457300037460974663680452494898918

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.730s	119.906us	1	1	100.00
V1	smoke	otp_ctrl_smoke	22.410s	7.006ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.410s	360.964us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.260s	601.592us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.740s	816.933us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	5.840s	161.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.380s	1.642ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.260s	601.592us	20	20	100.00
		otp_ctrl_csr_aliasing	5.840s	161.117us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.030s	547.695us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.970s	512.232us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	23.070s	1.536ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.940s	3.331ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.251m	31.681ms	10	10	100.00
		otp_ctrl_check_fail	1.360m	18.996ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.200s	4.308ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	44.580s	8.009ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	47.060s	1.523ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	39.060s	11.991ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	54.810s	17.719ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.152m	17.794ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	50.680s	9.999ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	8.280m	57.108ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	1.930s	545.056us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.960s	744.551us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.060s	2.892ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.060s	2.892ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.410s	360.964us	5	5	100.00
		otp_ctrl_csr_rw	2.260s	601.592us	20	20	100.00
		otp_ctrl_csr_aliasing	5.840s	161.117us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.540s	2.003ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.410s	360.964us	5	5	100.00
		otp_ctrl_csr_rw	2.260s	601.592us	20	20	100.00
		otp_ctrl_csr_aliasing	5.840s	161.117us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.540s	2.003ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
		otp_ctrl_tl_intg_err	33.510s	19.911ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	33.510s	19.911ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	22.410s	7.006ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	22.410s	7.006ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
		otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
		otp_ctrl_macro_errs	1.152m	17.794ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
		otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
		otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
		otp_ctrl_macro_errs	1.152m	17.794ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.120s	5.276ms	200	200	100.00
		otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.940s	3.331ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.360m	18.996ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	44.580s	8.009ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	44.580s	8.009ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	44.580s	8.009ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	44.580s	8.009ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	44.580s	8.009ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	22.410s	7.006ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	44.580s	8.009ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	22.410s	7.006ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.779m	154.840ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.200s	4.308ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	22.410s	7.006ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	22.410s	7.006ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.152m	17.794ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	18.020s	3.076ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.252h	208.939ms	87	100	87.00
V3		TOTAL			88	101	87.13
		TOTAL			1330	1343	99.03

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.72	93.81	96.13	95.69	90.93	97.00	96.33	93.14

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 8 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 8 failures.
  - 18.otp_ctrl_stress_all_with_rand_reset.79819931184153818316829042060840072400823723193314561504278919864521730459078
    Line 537, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2724921142 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 2724921142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.otp_ctrl_stress_all_with_rand_reset.19462286247025691737663603003134879122285226855470877050437235547787714736440
    Line 360, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  68772674 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @  68772674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

19.otp_ctrl_stress_all_with_rand_reset.18814839855743135099210061511924603923593546119564979247413123285944904782087
Line 30972, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 388783796601 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 388787629942 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 388787963276 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 388806129979 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 388806296646 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

50.otp_ctrl_stress_all_with_rand_reset.65038879596150771651217265419208470911659718510700675571256099053144777761849
Line 34309, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 53799236896 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 53799476896 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 53799496896 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 53799916896 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 53800096896 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 2 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 2 failures.
  - 45.otp_ctrl_stress_all_with_rand_reset.39631693913116783484948434313030287754749760341383404676502198978298949075754
    Line 6892, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20892375700 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (685382897 [0x28da1cf1] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 20892375700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.otp_ctrl_stress_all_with_rand_reset.54198268081921829152045798204832040858168546435963285239683370798980918826418
    Line 48601, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13238523870 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (472706120 [0x1c2cec48] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 13238523870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 98.otp_ctrl_stress_all_with_rand_reset.112105686634379530853953691985063845691646466406072716377605178005231758994546
    Line 52368, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 206278116443 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 36 [0x24]) dai addr 24 rdata0 readout mismatch
  UVM_INFO @ 206278116443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```