OTP_CTRL Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: `32d52b8d41`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	1.740s	67.955us	1	1	100.00
V1	smoke	otp_ctrl_smoke	23.550s	2.765ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.680s	1.082ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.830s	535.663us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.590s	846.015us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.370s	770.053us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.550s	411.869us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.830s	535.663us	20	20	100.00
		otp_ctrl_csr_aliasing	6.370s	770.053us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.520s	503.605us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.630s	565.918us	5	5	100.00
V1		TOTAL			116	116	100.00
V2	dai_access_partition_walk	otp_ctrl_partition_walk	22.310s	5.072ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.430s	2.549ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	56.710s	16.865ms	10	10	100.00
		otp_ctrl_check_fail	1.847m	13.479ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	15.190s	4.455ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.333m	12.873ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	52.360s	7.604ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	38.080s	9.426ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	45.930s	2.585ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	1.253m	21.426ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.015m	6.450ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	6.574m	57.145ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.080s	535.675us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.760s	859.533us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	8.310s	3.510ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	8.310s	3.510ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.680s	1.082ms	5	5	100.00
		otp_ctrl_csr_rw	1.830s	535.663us	20	20	100.00
		otp_ctrl_csr_aliasing	6.370s	770.053us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.090s	1.858ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.680s	1.082ms	5	5	100.00
		otp_ctrl_csr_rw	1.830s	535.663us	20	20	100.00
		otp_ctrl_csr_aliasing	6.370s	770.053us	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.090s	1.858ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
		otp_ctrl_tl_intg_err	30.940s	18.902ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	30.940s	18.902ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	23.550s	2.765ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	23.550s	2.765ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
		otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
		otp_ctrl_macro_errs	1.253m	21.426ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
		otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
		otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
		otp_ctrl_macro_errs	1.253m	21.426ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	46.250s	13.766ms	200	200	100.00
		otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.430s	2.549ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.847m	13.479ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.333m	12.873ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.333m	12.873ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.333m	12.873ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.333m	12.873ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.333m	12.873ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	23.550s	2.765ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.333m	12.873ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	23.550s	2.765ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.957m	154.699ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.190s	4.455ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	23.550s	2.765ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	23.550s	2.765ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	1.253m	21.426ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	16.650s	7.675ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	1.289h	2.263s	74	100	74.00
V3		TOTAL			75	101	74.26
		TOTAL			1317	1343	98.06

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.87	93.95	96.23	95.83	91.41	97.15	96.33	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 12 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 12 failures.
  - 8.otp_ctrl_stress_all_with_rand_reset.92156749941368758222969563233015183945848152028719509601808792318358165734008
    Line 45611, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17173330817 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 17173330817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.otp_ctrl_stress_all_with_rand_reset.16576148286720549733531485418042574398233670037771212801403871165966209678541
    Line 31699, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 80976633164 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 80976633164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 9 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 9 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.65850354625150913133733532070380706448727291421322127015769846464448135595801
    Line 7862, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6698871438 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1350568452 [0x50800a04] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 6698871438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.otp_ctrl_stress_all_with_rand_reset.63225851456588647379008198938250567825267288721071922276163595779668045329917
    Line 16440, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52291238285 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (447049881 [0x1aa57099] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 52291238285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 2 failures:

Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

6.otp_ctrl_stress_all_with_rand_reset.32548297207629492820474926800964079240170358617370052750079820359723952988660
Line 3079, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 490990935 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 491053437 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 491074271 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 491397198 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 491470117 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

73.otp_ctrl_stress_all_with_rand_reset.100048277652403041057678590192212115497451553358011557240128455695634157623240
Line 376, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 20070679574 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 20071679574 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 20071799574 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 20072759574 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 20072759574 ps: (dv_base_reg.sv:325) [otp_ctrl_core_reg_block.direct_access_regwen] lock_lockable_flds          0 val

UVM_ERROR (cip_base_vseq.sv:828) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 43.otp_ctrl_stress_all_with_rand_reset.48342273262946076906057420348775335934338335812731705781921609632600037762806
    Line 31732, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38149255642 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 38149255642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(cio_test_en_o == *)' has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 47.otp_ctrl_stress_all_with_rand_reset.24958922911533785797294755144073302924570036020401920962719721178457616679133
    Line 360, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 1030589713 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 1030589713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 64.otp_ctrl_stress_all_with_rand_reset.97223549835638489388228406449323057981807599989222544001729693403101749388427
    Line 13753, in log /container/opentitan-public/scratch/os_regression/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16442184444 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1324 [0x52c]) dai addr 52c rdata0 readout mismatch
  UVM_INFO @ 16442184444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```